Showing papers by "Mohamed I. Elmasry published in 1992"

STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits

Abstract: STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits that conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solve unit that dynamically integrates analytical model equations across hierarchical boundaries. The output of the solver is a flattened homogeneous model that is customized to a user-specified topology and set of performance specifications. The output is thus tailored for optimization and other numerically intense design exploration procedures. All model descriptions include physical layout so that important net parasitics may be fully accounted for during design evaluation. Synthesis proceeds via a successive solution refinement methodology. Multilevel models of increasing sophistication are used by scan and optimization modules to converge to what is likely a globally optimal solution. Design experiments have shown that STAIC can produce satisfactory results. >

Optimal synthesis of high-performance architectures

Abstract: An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and buses, is presented for synthesizing cost-constrained globally optimal architectures. This research is important to industry because it provides optimal schedules that minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high-performance architectures. A mathematical IP model of the architectural synthesis problem is formulated. A subset of the constraints is transformed into the node-packing problem and integral facets are extracted and generalized. Other constraints are tightened or mapped into the knapsack problem and facets are extracted and generalized. Area-delay cost functions are minimized using branch and bound on the resulting IP model. Globally optimal architectures are synthesized in faster CPU times than in previous research. >

Digital BiCMOS Integrated Circuit Design

Abstract: Preface. List of Symbols. 1. Introduction. 2. Process Technology. 3. Device Design Considerations. 4. Device Modeling. 5. MOS Digital Integrated Circuits. 6. Bipolar CML Integrated Circuits. 7. BiCMOS Digital Integrated Circuits. 8. BiCMOS Digital Circuit Applications. Subject Index.

Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits

Abstract: The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented. >

Optimization of digital BiCMOS circuits, an overview

Abstract: An overview of the optimization of buffer chains and multilevel logic in a BiCMOS environment, including scaling effects, is presented. The BiCMOS speed-up contours are reviewed. The use of these contours and analytical delay expressions in the design and optimization of BiCMOS buffer chains is also reviewed. The performance differences between different types of multi-stage mixed CMOS/BiCMOS buffers are summarized. Different BiCMOS current-mode logic (CML) circuits, such as the multi-emitter BiCMOS CML circuits, are considered. The performance advantages of using such circuits in implementing multilevel logic are summarized. >

Multiemitter BiCMOS CML circuits

Abstract: New BiCMOS current-mode logic (CML) circuits employing multiemitter devices are proposed. They perform logic functions in addition to conversion from CMOS to CML (or ECL). Their transient behavior was analyzed, and their delay expressions were obtained and verified using HSPICE. These expressions were used to optimize their design. Their performance s compared with other BiCMOS CML circuits with similar functionality. >

Low-voltage scaled CMOS and BiCMOS digital circuits

Abstract: A mixed two-dimensional numerical device/circuit simulation analysis of scaled BiCMOS and CMOS circuits is presented. Submicrometer processes with 0.4- mu m design rules operating at a power supply down to 2.8 V are examined. It is shown that when subjected to scaling, conventional BiCMOS maintains its superior performance compared to that of CMOS even at scaled power supplies. >

Design and optimization of buffer chains and logic circuits in a BiCMOS environment

Abstract: The design and optimization of BiCMOS buffer chains and multi level logic circuits are reported. BiCMOS speedup contours are introduced and analytical expressions for the delay are obtained. The speedup contours and the delay expressions were used in the design and optimization of BiCMOS buffer chains. Also, general design guidelines, which can be easily automated, for circuit design in a BiCMOS environment are given. Designing multistage mixed CMOS/BiCMOS buffers, BiCMOS complex logic gates, and multi level CML (current mode logic) gates is also studied. >

Analytical and numerical analyses of the delay time of BiCMOS structures

Abstract: Analytical expressions for the transient response of BiCMOS structures have been derived. The analysis is performed on conventional structures and structures employing short-channel MOSFETs. The equations relate the delay time to key device and technology parameters. In deriving the time response, the two basic conduction regions (linear and saturation) for the MOSFET have been considered. A numerical algorithm for solving for the delay time of BiCMOS structures taking into account high-level injection effects, base resistance, doping-dependent mobilities, and bandgap narrowing is presented. A figure of merit for the speed is derived and scaling the supply voltage is considered. >

Novel CMOS sampled-data VLSI implementation of artificial neural networks

Abstract: A mixed-mode VLSI implementation of artificial neural networks offers a tradeoff solution for speed, area saving, and flexibility. In the Letter, a novel CMOS sampled-data programmable synapse and a simple CMOS analogue neuron have been developed. Using a 1.2μm CMOS technology, the synapse consumed 120 × 120μm2 and the neuron consumed 120 × 260 μm2.

Mutual information training and size minimization of adaptive probabilistic neural networks

Abstract: An upper bound of the Bayes error probability is used as a generalized performance criterion for supervised neural network classifiers. It is shown that the maximization of the mutual information is equivalent to the minimization of this bound, which leads to a direct implementation of the Bayes framework for classification. The criterion is used both in training neural networks and in minimizing their size by adaptive pruning. A top-down heuristic for adaptively pruning oversized networks is proposed and applied. The approach is applied to adaptive probabilistic neural networks. Two benchmark problem results are given, verifying its validity. >

Introduction to Integer Programming

Abstract: General integer programming (IP) applications and solutions are briefly reviewed in this chapter. Section 4.1 outlines general formulation techniques for IP. Section 4.2 discusses state of the art solutions of general IP problems including classical enumerative and heuristic approaches (ie. simulated annealing). Recent successes in polyhedral approaches to solving partially structured IPs are outlined in section 4.3. Finally the definition and partial structure of the node packing problem (the focus of architectural synthesis) is given in section 4.4. (The notation for a graph is G=(V,E), where V is the set of vertices and E is the set of edges).

A pipelined VLSI arithmetic architecture

Abstract: A pipelined VLSI arithmetic architecture (PVAA), based on binary trees drawn from truth tables and matched to a dynamic logic cell (DLC), is presented. The modeling height reduction and multioutput logic of a DLC are discussed. Two typical switching tree structures, layered tree and sub-tree are developed. The latter covers three types of designs, i.e., serial, parallel, and pyramid. Several examples for different applications are given, and simulation results are obtained to illustrate the effectiveness of the PVAA. >

A methodology for selection of analog hardware for back-propagation algorithm implementation

Abstract: A methodology is presented for the selection of analog hardware components for the VLSI implementation of the backpropagation learning algorithm. The methodology makes use of a combination of theoretical analysis of error due to analog hardware non-idealities, as well as a procedure for modeling of the behaviour of these non-idealities. The theoretical analysis provides upper bounds on the errors for successful learning as well as for successful recognition of unknown patterns after learning has been completed. The modeling procedure helps to translate the errors due to hardware non-idealities to a form suitable for the theoretical analysis procedure. The bounds derived from the theoretical analysis are verified by simulating the backpropagation algorithm for a sample application, with the errors contained in it. The theoretical bounds are found to agree with the simulation results. >

Maximum mutual information training of a neural predictive-based HMM speech recognition system

Abstract: A corrective training scheme based on the maximum mutual information (MMI) criterion is developed for training a neural predictive-based HMM (hidden Markov model) speech recognition system. The performance of the system on speech recognition tasks when trained with this technique is compared to its performance when trained using the maximum likelihood (ML) criterion. Preliminary results obtained indicate the superiority of ML training over MMI training for predictive-based models. This result is in agreement with earlier findings in the literature regarding direct classification models. >

A VLSI neural network design approach using a priori knowledge

Abstract: Analyzing neural network (NN) algorithms, a priori knowledge can be often obtained from: the number of classes in pattern classification; the patterns in content-addressable memory: the coefficients in the element, e.g., weight value; and the adapting patterns in layered networks. The passive procedures to embody such knowledge can be implemented by lookup table technology. A NN design approach using such knowledge is described. Three typical structures, including output, input, and the learning model, are discussed. Their NN designs are accompanied by the corresponding lookup table technology. Compared with the traditional NN implementations, it is shown that this approach reduces VLSI complexity, while maintaining the same high performance. Examples of several applications are used to illustrate the effectiveness of the approach. >