Mohammad H. Naderi

TL;DR: The proposed technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high SR is demanded by large signals, which results in more than 45% reduction in slew time, and a 28% shorter slew time for 1% settling time when used in a typical 4.5 bit/stage block commonly used in pipelined analog-to-digital converters.

TL;DR: This study puts forward a strategy for optimal power sharing control in a microgrid that is connected to a utility grid through a back-to-back (B2B) converter, for which particle swarm optimization is used to optimally calculate the parameters of the system and the controllers.

TL;DR: This paper presents a 12-bit 500 MS/s pipelined ADC fabricated in the 40 nm TSMC technology, which aims to reduce the power consumption associated with residue amplifiers and comparator cells and proposes a forecasting technique in the sub-ADC, which reduces the number of active comparators during the sub theADC’s conversion phase.

TL;DR: An on-demand current source module: the bang–bang transient performance enhancer (BBTPE), which is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator.

TL;DR: The minimum total required transconductance for the different architectures of the pipelined ADC are computed and the Algorithmic-Pipelined architecture is shown to be more-tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture.