Методы подавления шумов и помех в электронных системах. (Noise reduction techniques in electronic systems)

Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

Noise on a dc power-bus that results from device switching, as well as other potential mechanisms, is a primary source of many signal integrity (SI) and electromagnetic interference (EMI) problems. Surface mount technology (SMT) decoupling capacitors are commonly used to mitigate this power-bus noise. A critical design issue associated with this common practice in high-speed digital designs is placement of the capacitors with respect to the integrated circuits (ICs). Local decoupling, namely, placing SMT capacitors in proximity to ICs, is investigated in this study. Multilayer PCB designs that employ entire layers or area fills for power and ground in a parallel plate structure are considered. The results demonstrate that local decoupling can provide high-frequency benefits for certain PCB geometries through mutual inductive coupling between closely spaced vias. The associated magnetic flux linkage is between the power and ground layers. Numerical modeling using an integral equation formulation with circuit extraction is used to quantify the local decoupling phenomenon. Local decoupling can effectively reduce high-frequency power-bus noise, though placing capacitors adjacent to ICs may limit routing flexibility, and tradeoffs need to be made based on design requirements. Design curves are generated as a function of power-bus layer thickness and SMT capacitor/IC spacing using the modeling approach to quantify the power-bus noise reduction for decoupling capacitors located adjacent to devices. Measurement data is provided to corroborate the modeling approach.

/pdf/quantifying-smt-decoupling-capacitor-placement-in-dc-power-stdv0smn88.pdf

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

As circuit boards are increasingly required to transmit signals at higher and higher speeds, signal and power integrity become increasingly crucial. Rules of thumb that you have used over and over again to prevent signal loss no longer apply to these new, high-speed, high-density circuit designs. This leading-edge circuit design resource offers you the knowledge needed to quickly pinpoint transmission problems that can compromise your entire circuit design. Discussing both design and debug issues at gigabit per second data rates, the book serves as a practical reference for your projects involving high-speed serial signaling on printed wiring boards. Step-by-step, this book goes from reviewing the essentials of linear circuit theory, to examining practical issues of pulse propagation along lossless and lossy transmission lines. It provides detailed guidelines for crosstalk, attenuation, power supply decoupling, and layer stackup tradeoffs (including pad/antipad tradeoffs). Other key topics include the construction of etched conductors, analysis of return paths and split planes, microstrip and stripline characteristics, and SMT capacitors. Filled with on-the-job-proven examples, this hands-on reference is the book that you can turn to time and again to design out and troubleshoot circuit signal loss and impedance problems.

High-speed circuit board signal integrity

Investigation of a dc power delivery network, consisting of a multilayer PCB using area fills for power and return, involves the distributed behavior of the power/ground planes and the parasitics associated with the lumped components mounted on it Full-wave methods are often employed to study the power integrity problem While full-wave methods can be accurate, they are time and memory consuming The cavity model of a rectangular structure has previously been employed to efficiently analyze the simultaneous switching noise (SSN) in the power distribution network However, a large number of modes in the cavity model are needed to accurately simulate the impedance associated with the vias, leading to computational inefficiency A fast approach is detailed herein to accelerate calculation of the summation associated with the higher-order modes Closed-form expressions for the parasitics associated with the interconnects of the decoupling capacitors are also introduced Combining the fast calculation of the cavity models of regularly shaped planar circuits, a segmentation method, and closed-form expressions for the parasitics, an efficient approach is proposed herein to analyze an arbitrary shaped power distribution network While it may take many hours for a full-wave method to do a single simulation, the proposed method can generally perform the simulation with good accuracy in several minutes Another advantage of the proposed method is that a SPICE equivalent circuit of the power distribution network can be derived This allows both frequency and transient responses to be done with SPICE simulation

/pdf/an-efficient-approach-for-power-delivery-network-design-with-3o4etjfbpy.pdf

An efficient approach for power delivery network design with closed-form expressions for parasitic interconnect inductances

The decoupling capacitor location in DC power bus design is a critical design choice for which proven guidelines are not well established. The mutual inductance between two closely spaced vias can have a great impact on the coupling between an IC and a decoupling capacitor. This coupling is a function of the spacing between the IC and capacitor, and spacing between power and ground layers. The impact of the mutual inductance on decoupling, i.e., local versus global decoupling, was studied, using a circuit extraction approach based on a mixed-potential integral equation. Modeling indicates that local decoupling has benefits over global decoupling for certain ranges of IC/capacitor spacing and power layer thickness. Design curves for evaluating local decoupling benefits were generated, which can be used to guide surface mount technology (SMT) decoupling capacitor placement.

https://scholarsmine.mst.edu/cgi/viewcontent.cgi?article=2843&context=ele_comeng_facwork

Quantifying decoupling capacitor location

Vias in differential transmission lines have been modeled using the finite-difference time-domain (FDTD) method. The velocity that the differential signal propagated through the vias was estimated. Differential S-parameters were calculated up to 50 GHz. Below 10 GHz, the differential signal can propagate through vias without much reflection and distortion. However, as frequency increases, the reflection from the vias and the loss of differential power become significant.

/pdf/the-effects-of-via-transitions-on-differential-signals-1bpbxq0u90.pdf

The effects of via transitions on differential signals

The modeling and the analysis of the power distribution networks (PDN) within multi-layer printed circuit board is crucial for the investigation of the performance of PCB systems. Carrying out such analyses in SPICE based tools has the advantage of being faster than the corresponding full-wave modeling and it allows obtaining both frequency and time domain results.

/pdf/complex-power-distribution-network-investigation-using-spice-25x74787zu.pdf

Complex power distribution network investigation using SPICE based extraction from first principle formulations

This paper introduces an approach of using a plated through-hole (PTH) via transmission-line model in the design of a thick printed circuit board, such as a backpanel. Full wave FEM modeling of a section of backpanel containing a differential via pair was compared with a transmission model. Computed values of the differential transmission loss agreed within an acceptable range for engineering studies, yet the transmission line model results required less than 2% of the computation time that the full wave model required. Effects of via spacing, via diameter and trace thickness were also examined.

/pdf/application-of-transmission-line-models-to-backpanel-plated-522dvqm35q.pdf

N.W. Smith

Papers

Quantifying SMT decoupling capacitor placement in dc power-bus design for multilayer PCBs

Quantifying decoupling capacitor location

The effects of via transitions on differential signals

Complex power distribution network investigation using SPICE based extraction from first principle formulations

Application of transmission line models to backpanel plated through-hole via design