Naresh R. Shanbhag

TL;DR: A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm, and a full-decoder architecture is presented.

TL;DR: It is now possible to fabricate wireless, battery-free vital signs monitoring systems based on ultrathin, “skin-like” measurement modules that can gently and noninvasively interface onto the skin of neonates with gestational ages down to the edge of viability.

TL;DR: New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented, which require approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm.

TL;DR: A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations, and algorithmic noise-tolerance schemes can also be used to improve theperformance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.

TL;DR: A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented, which implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm.