N
Naresh R. Shanbhag
Researcher at University of Illinois at Urbana–Champaign
Publications - 335
Citations - 10118
Naresh R. Shanbhag is an academic researcher from University of Illinois at Urbana–Champaign. The author has contributed to research in topics: Adaptive filter & CMOS. The author has an hindex of 49, co-authored 325 publications receiving 9202 citations. Previous affiliations of Naresh R. Shanbhag include Bell Labs & Wright State University.
Papers
More filters
Journal ArticleDOI
High-throughput LDPC decoders
TL;DR: A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm, and a full-decoder architecture is presented.
Journal ArticleDOI
Binodal, wireless epidermal electronic systems with in-sensor analytics for neonatal intensive care
Ha Uk Chung,Bong Hoon Kim,Jong Yoon Lee,Jungyup Lee,Zhaoqian Xie,E. Ibler,E. Ibler,Kun Hyuck Lee,Anthony Banks,Ji Yoon Jeong,Jongwon Kim,Jongwon Kim,Christopher Ogle,Dominic Grande,Yongjoon Yu,Hokyung Jang,Pourya Assem,Dennis Ryu,Jean Won Kwak,Myeong Namkoong,Jun Bin Park,Yechan Lee,Do Hoon Kim,Arin Ryu,Jaeseok Jeong,Kevin You,Bowen Ji,Zhuangjian Liu,Qingze Huo,Xue Feng,Yujun Deng,Yujun Deng,Yeshou Xu,Yeshou Xu,Kyung In Jang,Jeonghyun Kim,Yihui Zhang,Roozbeh Ghaffari,Casey M. Rand,Molly Schau,Aaron Hamvas,Debra E. Weese-Mayer,Yonggang Huang,Seungmin Lee,Chi Hwan Lee,Naresh R. Shanbhag,Amy S. Paller,Amy S. Paller,Shuai Xu,John A. Rogers +49 more
TL;DR: It is now possible to fabricate wireless, battery-free vital signs monitoring systems based on ultrathin, “skin-like” measurement modules that can gently and noninvasively interface onto the skin of neonates with gestational ages down to the edge of viability.
Journal ArticleDOI
High-speed architectures for Reed-Solomon decoders
TL;DR: New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented, which require approximately 25% fewer multipliers and a simpler control structure than the architectures based on the popular extended Euclidean algorithm.
Journal ArticleDOI
Soft digital signal processing
R. Hegde,Naresh R. Shanbhag +1 more
TL;DR: A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations, and algorithmic noise-tolerance schemes can also be used to improve theperformance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.
Journal ArticleDOI
A 640-Mb/s 2048-bit programmable LDPC decoder chip
TL;DR: A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented, which implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm.