P
Pooja R. Batra
Researcher at IBM
Publications - 9
Citations - 78
Pooja R. Batra is an academic researcher from IBM. The author has contributed to research in topics: Dram & Chip. The author has an hindex of 6, co-authored 9 publications receiving 75 citations.
Papers
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Journal ArticleDOI
Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology
Pooja R. Batra,Spyridon Skordas,Douglas Charles Latulipe,Kevin R. Winstel,Chandrasekharan Kothandaraman,Ben Himmel,Gary W. Maier,Bishan He,Deepal Wehella Gamage,John W. Golz,Wei Lin,Tuan Vo,Deepika Priyadarshini,Alex Hubbard,Kristian Cauffman,B. Peethala,John E. Barth,Toshiaki Kirihata,Troy L. Graves-Abe,Norman Robson,Subramanian S. Iyer +20 more
TL;DR: In this paper, the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery.
Proceedings ArticleDOI
Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology
Pooja R. Batra,Douglas Charles Latulipe,Spyridon Skordas,Kevin R. Winstel,Chandrasekharan Kothandaraman,Ben Himmel,Gary W. Maier,Bishan He,Deepal Wehella Gamage,John W. Golz,Wei Lin,Tuan Vo,Deepika Priyadarshini,Alex Hubbard,Kristian Cauffman,B. Peethala,John E. Barth,Toshiaki Kirihata,Troy L. Graves-Abe,Norman Robson,Subramanian S. Iyer +20 more
TL;DR: In this article, the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45nm SOI-CMOS embedded DRAM (EDRAM) having 12 to 13 copper wiring levels per strata.
Journal ArticleDOI
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
Toshiaki Kirihata,John Golz,Matthew R. Wordeman,Pooja R. Batra,Gary W. Maier,Norman Robson,Troy L. Graves-Abe,Daniel Berger,Subramanian S. Iyer +8 more
TL;DR: 3D DRAMs including DDR3, wide I/O mobile DRAM, and more recently, the hybrid-memory cube (HMC) and high-bandwidth memory (HBM) targeted for high-performance computing systems are reviewed.
Proceedings ArticleDOI
Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects
Wei Lin,Johnathan E. Faltermeier,Kevin R. Winstel,Spyridon Skordas,Troy L. Graves-Abe,Pooja R. Batra,Kenneth Robert Herman,John W. Golz,Toshiaki Kirihata,John J. Garant,Alex Hubbard,Kris Cauffman,Theodore Levine,James J. Kelly,Deepika Priyadarshini,B. Peethala,Raghuveer R. Patlolla,Matthew T. Shoudy,James J. Demarest,Jean E. Wynne,Donald F. Canaperi,D. McHerron,Daniel Berger,Subramanian S. Iyer +23 more
TL;DR: In this article, a proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects is reported.
Patent
Double-sided segmented line architecture in 3d integration
TL;DR: In this article, a double-sided three-dimensional (3D) hierarchal architecture for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring is presented.