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Technical manual : 日本語版

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

Ferroelectric Negative Capacitance Field Effect Transistor

We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current ( ${I}_{ \mathrm{OFF}}$ ) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$ . On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$ . Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes.

Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO 2 Oxide

Fully depleted silicon-on-insulator (FDSOI) MOSFET-based inverter is used as a distance computing cell (DCC) for non-Boolean associative processing system. Using back-gate bias in FDSOI transistors, the DCC shows excellent controllability of current characteristics of DCC. The system consumes 150 to 300 times lower energy than bulk CMOS-based Boolean implementation and requires lesser number of transistors. It also consumes lower area and energy than most of the other non-Boolean systems. Additionally, output voltage swing, recognition accuracy, and consumed energy in the system, can be controlled by applying proper back gate voltage, on the transistors of winner take all block and DCC.

Non-Boolean Associative Processing Using FDSOI MOSFET-Based Inverter

The continuous reduction in the thickness of body and BOX of FDSOI MOS devices (to sustain scaling) have resulted in increased coupling between the top-gate and substrate underneath BOX. In this work, we have reported an increase in small signal trans-conductance (g m ) with increase in frequency because of this coupling. This dependence is modulated by changing the substrate doping and BOX thickness. The physical mechanism responsible for this behavior is explained through measurement on different test structures and detailed device simulation.

Impact of substrate on the frequency behavior of trans-conductance in ultrathin body and BOX FDSOI MOS devices - a physical insight

Lateral nanosheet field-effect-transistor (FET) is now targeting for 3nm CMOS technology node [1], [2]. It is important to see quantization effect at such confined geometry. In this work, we study the geometrical confinement effects in silicon nanosheet. We developed a unified phenomenological model for insulator capacitance (C ins ) in rectangular (i.e., Nanosheet) cross-section gate-all-around (GAA) FET to solve the gate charge density accurately. It is observed that multi-subband conduction causes humps in higher order derivatives of charge vs gate voltage characteristics which may affect the performance of analog and RF circuits.

Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET

High power operation of AlGaN/GaN HEMTs leads to a high channel temperature and heat dissipation issues which severely degrade the device reliability and power performance. Self-heating effects cannot be ignored when estimating the power performance of HEMTs, and have been an active area of research for a long time [1], [2]. Several methods used for thermal resistance measurements have been proposed in the literature, including techniques to generate comprehensive temperature profiles like infrared thermography, high-resolution Raman thermography [3], [4], etc. These thermography approaches are not always practical as they frequently require specific device samples and prohibitively expensive laboratory equipment. Pulsed measurements enable the determination of thermal resistance across a wide range of ambient temperatures [5], [6] and have been used in this work. The industry standard compact models [7]–[9] account for the self-heating effect using a thermal circuit approach involving parallel RC circuits to represent thermal time constants as shown in Fig 2(c). However, these self-heating models are valid for a narrow range of geometries and are not scalable in the truest sense (as shown in Fig. 1(a)). In this paper we presents a complete SPICE model capable of emulating the geometry-dependent self-heating behavior using a single model card.

A width-scalable SPICE compact model for GaN HEMTs including self-heating effect

In this work, we present a phenomenological cryogenic model for gallium nitride (GaN) high electron mobility transistors (HEMTs) with validity all the way down to a temperature of 10 K, benchmarked with experimental characterization results. The device under test (DUT) for cryogenic characterization is a GaN HEMT with a channel length of 250 nm and a gate width of <inline-formula> <tex-math notation="LaTeX">$40~\mu \text{m}$ </tex-math></inline-formula>. The characterization results exhibit the negative threshold voltage shifts of −3.437, −3.087, and −2.998 V at the temperatures of 300, 60, and 10 K, respectively. Additionally, kink effects at cryogenic temperatures in output characteristics are observed that behave non-monotonically with gate-to-source bias. The impact of detrapping is modeled to investigate the negative shift in <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> with increasing temperature. To model the kink, the effects of temperature, impact ionization, and field-dependent trapping/detrapping on <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> have been explored and implemented as a submodel in the industry standard Advanced SPICE Model (ASM)-HEMT framework. Here, we aim to overcome the limitations of the prior GaN device models in the quest for enabling GaN-based circuits for cryogenic applications, such as deep space reception, radio astronomy, and quantum computing.

Pragya Kushwaha

Papers

Non-Boolean Associative Processing Using FDSOI MOSFET-Based Inverter

Impact of substrate on the frequency behavior of trans-conductance in ultrathin body and BOX FDSOI MOS devices - a physical insight

Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET

A width-scalable SPICE compact model for GaN HEMTs including self-heating effect

Electrical Characterization and Modeling of GaN HEMTs at Cryogenic Temperatures