This article presents an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN). The deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition. A power series method is used to solve differential equations for different regions of transistors during output transition. The PSN has been expressed in Taylor series expression, aids to derive closed-form equation for time interval error (TIE). The obtained results from the proposed methodology closely match with electronic design automation (EDA) simulator results and verified on 40 nm Taiwan Semiconductor Manufacturing Company (TSMC) and 28 nm United Microelectronics Corporation (UMC) foundries, demonstrating accurate modeling of jitter.

Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters

This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers. The requirements of nonlinear modeling for the accurate prediction is explained and illustrated. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum values of the prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

This paper presents an analysis of jitter due to various deterministic noise sources in a CMOS inverter. The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained from full SPICE based simulations. For the estimation of jitter, EMPSIJ method [1] is used in the paper. The paper also discusses the sensitivity of various noise paths on jitter.

Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter

This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.

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A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.

Efficient Jitter Analysis for a Chain of CMOS Inverters

This paper presents an analytical approach to evaluate jitter in the CMOS inverters caused by the periodic fluctuations of the power supply. A closed-form equation of time interval error (TIE) is derived that uses device model parameters to calculate it. In order to derive the output expression for an inverter for various regions of operation which appears during the transition edges, a power series expansion method is used. For the purpose of validation, a 40 nm Ultra Low Power (ULP) commercial technology of TSMC is used with V DD of 1.2 V. The results obtained from the proposed analytical model are verified by comparing them with the simulation results obtained from a standard electronic design automation (EDA) tool, demonstrating an accurate modeling of jitter.

Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations

In this paper, we propose a new multiplexer-based frequency selector for designing area-efficient phase locked loop (PLL) for frequency synthesis. Such reduction in the design area has been achieved by replacing conventional capacitor array in voltage controlled oscillator of this PLL by multiplexor based frequency selector. Subsequently, it has been coupled with the current-reuse voltage-controlled oscillator to reduce overall phase noise of PLL to a considerable extent. Additionally, the proposed PLL circuitry is capable of self-bandwidth switching and it is suitable for applications requiring multiple frequency bands and fast settling time. Circuit implementation of this PLL performed at 130 nm-CMOS technology-node resulted in the design area of 0.037 mm2, power consumption of 360µW at 0.9 GHz and a settling time of 22 µS. In comparison with the state-of-the-art implementations, our design occupies 98% smaller area and consumes 50% lesser power.

Puneet Arora

Papers

Efficient Jitter Analysis for a Chain of CMOS Inverters

Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters

Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations

A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector