Q
Q. Liang
Researcher at IBM
Publications - 1
Citations - 58
Q. Liang is an academic researcher from IBM. The author has contributed to research in topics: Logic gate & High-κ dielectric. The author has an hindex of 1, co-authored 1 publications receiving 57 citations.
Papers
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Proceedings Article
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
Brian J. Greene,Q. Liang,K. Amarnath,Y. Wang,J. Schaeffer,M. Cai,Yue Liang,S. Saroop,J. Cheng,A. Rotondaro,Shu-Jen Han,R. Mo,K. McStay,S.H. Ku,R. Pal,Mahender Kumar,B. Dirahoui,B. Yang,F. Tamweber,Woo-Hyeong Lee,M. Steigerwalt,H. Weijtmans,Judson R. Holt,L. Black,S. Samavedam,M. Turner,K. Ramani,D. Lee,Michael P. Belyansky,M. Chowdhury,D. Aime,B. Min,H. van Meer,Haizhou Yin,K.K. Chan,M. Angyal,M. Zaleski,O. Ogunsola,C. Child,L. Zhuang,H. Yan,D. Permanaa,Jeffrey W. Sleight,Dechao Guo,S. Mittl,D. Ioannou,Ernest Y. Wu,Michael P. Chudzik,D.-G. Park,D. Brown,Scott Luning,Dan Mocuta,Edward P. Maciejewski,K. Henson,Effendi Leobandung +54 more
TL;DR: In this paper, a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2 is presented, enabling performance without the power penalty from gate capacitance.