K
K. McStay
Researcher at IBM
Publications - 2
Citations - 134
K. McStay is an academic researcher from IBM. The author has contributed to research in topics: CMOS & Silicon on insulator. The author has an hindex of 2, co-authored 2 publications receiving 133 citations.
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Proceedings ArticleDOI
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
Effendi Leobandung,H. Nayakama,Dan Mocuta,K. Miyamoto,M. Angyal,H.V. Meer,K. McStay,Ishtiaq Ahsan,Scott D. Allen,Atsushi Azuma,Michael P. Belyansky,R.-V. Bentum,J. Cheng,Dureseti Chidambarrao,B. Dirahoui,M. Fukasawa,M. Gerhardt,Michael A. Gribelyuk,Scott Halle,H. Harifuchi,D. Harmon,J. Heaps-Nelson,H. Hichri,K. Ida,M. Inohara,I.C. Inouc,Keith Jenkins,T. Kawamura,Byeong Y. Kim,S.-K. Ku,Mahender Kumar,S. Lane,Lars W. Liebmann,R. Logan,I. Melville,K. Miyashita,Anda Mocuta,P. O'Neil,M.-F. Ng,Takeshi Nogami,A. Nomura,Christine Norris,E. Nowak,Mizuki Ono,Siddhartha Panda,C. Penny,Carl J. Radens,Ravikumar Ramachandran,A. Ray,S.-H. Rhee,D. Ryan,T. Shinohara,G. Sudo,F. Sugaya,Jay W. Strane,Y. Tan,L. Tsou,L. K. Wang,F. Wirbeleit,S. Wu,Tenko Yamashita,H. Yan,Q. Ye,D. Yoneyama,D. Zamdmer,Huicai Zhong,Huilong Zhu,Wenjuan Zhu,Paul D. Agnello,Scott J. Bukofsky,Gary B. Bronner,Emmanuel F. Crabbe,G. Freeman,Shih-Fen Huang,T. Ivers,H. Kuroda,D. McHerron,J. Pellerin,Yoshiaki Toyoshima,S. Subbanna,N. Kepler,L. Su +81 more
TL;DR: In this article, a high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels.
Proceedings Article
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
Brian J. Greene,Q. Liang,K. Amarnath,Y. Wang,J. Schaeffer,M. Cai,Yue Liang,S. Saroop,J. Cheng,A. Rotondaro,Shu-Jen Han,R. Mo,K. McStay,S.H. Ku,R. Pal,Mahender Kumar,B. Dirahoui,B. Yang,F. Tamweber,Woo-Hyeong Lee,M. Steigerwalt,H. Weijtmans,Judson R. Holt,L. Black,S. Samavedam,M. Turner,K. Ramani,D. Lee,Michael P. Belyansky,M. Chowdhury,D. Aime,B. Min,H. van Meer,Haizhou Yin,K.K. Chan,M. Angyal,M. Zaleski,O. Ogunsola,C. Child,L. Zhuang,H. Yan,D. Permanaa,Jeffrey W. Sleight,Dechao Guo,S. Mittl,D. Ioannou,Ernest Y. Wu,Michael P. Chudzik,D.-G. Park,D. Brown,Scott Luning,Dan Mocuta,Edward P. Maciejewski,K. Henson,Effendi Leobandung +54 more
TL;DR: In this paper, a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2 is presented, enabling performance without the power penalty from gate capacitance.