E
Edward P. Maciejewski
Researcher at IBM
Publications - 47
Citations - 834
Edward P. Maciejewski is an academic researcher from IBM. The author has contributed to research in topics: Gate oxide & CMOS. The author has an hindex of 15, co-authored 47 publications receiving 806 citations. Previous affiliations of Edward P. Maciejewski include GlobalFoundries.
Papers
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Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Proceedings ArticleDOI
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
Shreesh Narasimha,Paul Chang,Claude Ortolland,David M. Fried,E. Engbrecht,Karen A. Nummy,Paul C. Parries,Takashi Ando,Michael V. Aquilino,N. Arnold,R. Bolam,Jin Cai,Michael P. Chudzik,Benjamin Cipriany,G. Costrini,Min Dai,Jessica Dechene,C. DeWan,Bernard A. Engel,Michael A. Gribelyuk,Dechao Guo,G. Han,N. Habib,Judson R. Holt,Dimitris P. Ioannou,Basanth Jagannathan,Jaeger Daniel,J. Johnson,W. Kong,J. Koshy,Rishikesh Krishnan,Amit Kumar,Mahender Kumar,Jae Gon Lee,Xiaolin Li,C-H. Lin,Barry P. Linder,S. Lucarini,Naftali E. Lustig,Paul S. McLaughlin,Katsunori Onishi,Viorel Ontalus,Robert R. Robison,Christopher D. Sheraw,Matthew W. Stoker,Alvin G. Thomas,Geng Wang,Richard Wise,L. Zhuang,Gregory G. Freeman,J. Gill,Edward P. Maciejewski,Rajeev Malik,J. Norum,Paul D. Agnello +54 more
TL;DR: A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability in SOI CMOS 22nm technology.
Proceedings ArticleDOI
RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology
Ishtiaq Ahsan,Noah Zamdmer,O. Glushchenkov,R. Logan,E. J. Nowak,H. Kimura,J. Zimmerman,G. Berg,J. Herman,Edward P. Maciejewski,Alvin T. S. Chan,Atsushi Azuma,Sadanand V. Deshpande,B. Dirahoui,Gregory G. Freeman,Allen H. Gabor,Michael A. Gribelyuk,Shih-Fen Huang,Mahender Kumar,K. Miyamoto,Dan Mocuta,Mahoro +21 more
TL;DR: In this article, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA), is presented.
Proceedings Article
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper
Brian J. Greene,Q. Liang,K. Amarnath,Y. Wang,J. Schaeffer,M. Cai,Yue Liang,S. Saroop,J. Cheng,A. Rotondaro,Shu-Jen Han,R. Mo,K. McStay,S.H. Ku,R. Pal,Mahender Kumar,B. Dirahoui,B. Yang,F. Tamweber,Woo-Hyeong Lee,M. Steigerwalt,H. Weijtmans,Judson R. Holt,L. Black,S. Samavedam,M. Turner,K. Ramani,D. Lee,Michael P. Belyansky,M. Chowdhury,D. Aime,B. Min,H. van Meer,Haizhou Yin,K.K. Chan,M. Angyal,M. Zaleski,O. Ogunsola,C. Child,L. Zhuang,H. Yan,D. Permanaa,Jeffrey W. Sleight,Dechao Guo,S. Mittl,D. Ioannou,Ernest Y. Wu,Michael P. Chudzik,D.-G. Park,D. Brown,Scott Luning,Dan Mocuta,Edward P. Maciejewski,K. Henson,Effendi Leobandung +54 more
TL;DR: In this paper, a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2 is presented, enabling performance without the power penalty from gate capacitance.
Patent
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
Atul C. Ajmera,Andres Bryant,Percy V. Gilbert,Michael A. Gribelyuk,Edward P. Maciejewski,Renee T. Mo,Shreesh Narasimha +6 more
TL;DR: In this article, a method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described, which also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide.