There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Micromachining and micro-electromechanical system (MEMS) technologies can be used to produce complex structures, devices and systems on the scale of micrometers. Initially micromachining techniques were borrowed directly from the integrated circuit (IC) industry, but now many unique MEMS-specific micromachining processes are being developed. In MEMS, a wide variety of transduction mechanisms can be used to convert real-world signals from one form of energy to another, thereby enabling many different microsensors, microactuators and microsystems. Despite only partial standardization and a maturing MEMS CAD technology foundation, complex and sophisticated MEMS are being produced. The integration of ICs with MEMS can improve performance, but at the price of higher development costs, greater complexity and a longer development time. A growing appreciation for the potential impact of MEMS has prompted many efforts to commercialize a wide variety of novel MEMS products. In addition, MEMS are well suited for the needs of space exploration and thus will play an increasingly large role in future missions to the space station, Mars and beyond. (Some figures in this article are in colour only in the electronic version)

https://iopscience.iop.org/article/10.1088/0964-1726/10/6/301/pdf

Microelectromechanical systems (MEMS):fabrication, design and applications

As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated with in the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved w thout significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits

/pdf/fault-model-generation-for-mems-7fqegt7dao.pdf

Fault Model Generation for MEMS

Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. To reduce the cost of evaluating new test metrics, fault models, DFT techniques, etc., this work proposes a new approach that exploits the readily-available test-measurement data in chip-failure log files. The new approach does not require the generation and application of new patterns but uses analysis results from existing tests. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) PAN-detect (physically-aware N-detect), (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).

Test effectiveness evaluation through analysis of readily-available tester data

Logic-level simulation has been the de facto method for simulating defect/faulty behavior for various testing tasks since it offers a good tradeoff between accuracy and speed. Unfortunately, by abstracting defect behavior to the logic level (i.e., a fault model), it also discards important information that inevitably results in inaccuracies. This paper describes a fast and accurate defect simulation framework called SLIDER (simulation of layout-injected defects for electrical responses). SLIDER uses well-developed mixed-signal simulation technology that is conventionally used for design verification. There are three innovative aspects that distinguish SLIDER from prior work in this area: 1) accuracy resulting from defect injection taking place at the layout level; 2) speedup resulting from careful and automatic partitioning of the circuit into maximal digital and minimal analog domains for mixed-signal simulation; and 3) complete automation that includes defect generation, defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The virtual failure data created by SLIDER is useful in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and evaluation of yield/test learning techniques that are based on failure data analysis.

SLIDER: Simulation of Layout-Injected Defects for Electrical Responses

Physically-aware N-detect (PAN-detect) test has been demonstrated to improve defect detection for modern designs. One existing approach for PAN-detect test generation that is applicable for industrial designs generates fully-specified test sets. This work presents a PAN-detect test relaxation methodology that can be applied to both physically-aware test sets as well as arbitrary test sets. The methodology enhances PAN-detect test applicability by allowing test-input values to be unspecified as don’t cares, which can be utilized for test compression, scan-power reduction, and test enrichment. The test quality of the relaxed test set is maintained by preserving the PAN-detect coverage of the original test set. Experiment results demonstrate that the physically-aware N-detect test relaxation approach relaxes, on average, 42% of the test-input values while preserving PAN-detect coverage.

R.D. Blanton

Papers

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits

Fault Model Generation for MEMS

Test effectiveness evaluation through analysis of readily-available tester data

SLIDER: Simulation of Layout-Injected Defects for Electrical Responses

Physically-Aware N-Detect Test Relaxation