There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Micromachining and micro-electromechanical system (MEMS) technologies can be used to produce complex structures, devices and systems on the scale of micrometers. Initially micromachining techniques were borrowed directly from the integrated circuit (IC) industry, but now many unique MEMS-specific micromachining processes are being developed. In MEMS, a wide variety of transduction mechanisms can be used to convert real-world signals from one form of energy to another, thereby enabling many different microsensors, microactuators and microsystems. Despite only partial standardization and a maturing MEMS CAD technology foundation, complex and sophisticated MEMS are being produced. The integration of ICs with MEMS can improve performance, but at the price of higher development costs, greater complexity and a longer development time. A growing appreciation for the potential impact of MEMS has prompted many efforts to commercialize a wide variety of novel MEMS products. In addition, MEMS are well suited for the needs of space exploration and thus will play an increasingly large role in future missions to the space station, Mars and beyond. (Some figures in this article are in colour only in the electronic version)

https://iopscience.iop.org/article/10.1088/0964-1726/10/6/301/pdf

Microelectromechanical systems (MEMS):fabrication, design and applications

Despite best efforts, integrated systems are “born” (manufactured) with a unique ‘personality’ that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the best-performing systems but this would result in unacceptable yields and correspondingly high costs. The system personality is further shaped by its environment (e.g., temperature, noise and supply voltage) and usage (i.e., the frequency and type of applications executed), and since both can fluctuate over time, so can the system's personality. Systems also “grow old” and degrade due to various wear-out mechanisms (e.g., negative-bias temperature instability), and unexpectedly due to various early-life failure sources. These “nature and nurture” influences make it extremely difficult to design a system that will operate optimally for all possible personalities. To address this challenge, we propose to develop statistical learning in-chip (SLIC). SLIC is a holistic approach to integrated system design based on continuously learning key personality traits on-line, for self-evolving a system to a state that optimizes performance hierarchically across the circuit, platform, and application levels. SLIC will not only optimize integrated-system performance but also reduce costs through yield enhancement since systems that would have before been deemed to have weak personalities (unreliable, faulty, etc.) can now be recovered through the use of SLIC.

/pdf/slic-statistical-learning-in-chip-2e3z5edz8r.pdf

SLIC: Statistical learning in chip

We address the problem of generating compact dictionaries for the diagnosis of unmodeled faults in scan-BIST. We present dictionary organization schemes that provide two orders of magnitude reduction in dictionary size with no significant loss in resolution, and facilitate the diagnosis of unmodeled faults. Experimental results for the ISCAS-89 benchmark circuits show that various types of unmodeled faults can be efficiently located using compact dictionaries generated for single stuck-at-faults.

/pdf/compact-dictionaries-for-diagnosis-of-unmodeled-faults-in-52eieaalyk.pdf

Compact dictionaries for diagnosis of unmodeled faults in scan-BIST

Inductive fault analysis techniques examine the physical geometry of a design to identify potential defect sites. Since traditional methodologies for test generation, fault simulation, and diagnosis rely on logic-level models of the circuit under test, the behavior of a circuit node within a standard cell is not easily modeled since it does not always map directly to a logic-level signal. A significant percentage of defects, however, involves these internal nodes and therefore cannot be ignored. Also, due to the potentially complex behavior of feedback bridges, many defects that cause structural feedback are ignored. We propose a methodology to create a mapping between the physical nodes of a standard cell and the logic level. By identifying appropriate fault activation and error propagation conditions for each internal node, accurate fault models can be formulated. We also describe a strategy for modeling feedback bridges that enables the use of traditional test tools.

Automated Standard Cell Library Analysis for Improved Defect Modeling

Software-based fault diagnosis has traditionally been used to assist the complex and time-consuming task of physical failure analysis (PFA) by providing target locations (gates, sub-circuits, or nets) However, the effectiveness of this two-stage approach is diminishing rapidly with the continuous circuit miniaturization and increasing complexity of the manufacturing process and packaging technology Coupled with the increased need for rapid yield learning, this has necessitated new techniques that maximize learning about defect characteristics at the software-based diagnosis level with the goal of reducing eliminating the dependence on PFA This research is a step towards addressing this growing need 
In this dissertation, we present a comprehensive diagnosis methodology and its implementation in a software tool, DIAGNOSIX, for characterizing the logic-behavior of IC failures The goal of DIAGNOSIX is to extract one or more fault models for the IC failures, where each fault model accurately captures the locations and behavior of the defects responsible for the observed failures Accurate characterization of logic-behavior becomes important under three scenarios First, if there are many failing ICs (during a yield excursion), then a fault diagnosis that provides accurate misbehavior information helps to identify and target the most critical defect mechanisms Second, the area to be analyzed during PFA is reduced if the diagnosis reports, for example, a bridge between two lines instead of a set of lines because in this case only the area where the lines are actually adjacent has to be inspected Third, identification of logic misbehavior can lead to development of accurate fault models, which can be used to improve defect coverage during future manufacturing test activities 
DIAGNOSIX is comprehensive because of two main reasons: (1) it is not limited by presumed models of defect behavior in the form of fault models, ie, rather than checking if an instance of a presumed fault model captures the observed defect behavior, DIAGNOSIX instead analyzes the CUT response to "extract" the fault(s) that model the defect behavior; and (2) it uses all the test patterns (both tester failing and tester passing patterns) and includes generation of additional test patterns to improve diagnosis accuracy, resolution and confidence, three metrics that we have formally defined 
Fault extraction in DIAGNOSIX is enabled by the use of limited layout information and the key assumption that defects are typically localized Specifically, DIAGNOSIX automatically extracts a fault model for a failing IC by analyzing the behavior of the physical neighborhood surrounding suspect lines The suspect lines themselves are identified using an initial, fault model-independent localization step

A comprehensive diagnosis methodology for characterizing logic-behavior of integrated circuit failures

Fault tuples have introduced a fault model independent methodology for digital circuit test analysis. However, the {0, 1, X} algebra currently used with fault tuples allows only one form of path sensitization. The sensitization options for fault tuples is enhanced based on a 5-value algebra. The 5-value algebra enables a more detailed test analysis through the selection of one of three types of sensitization. Simulation experiments performed using the ITC'99 benchmark circuits for transition and path delay faults reveal that faults can be simultaneously analyzed under different types of sensitization criteria with little increase in memory and CPU time.

R.D. Blanton

Papers

SLIC: Statistical learning in chip

Compact dictionaries for diagnosis of unmodeled faults in scan-BIST

Automated Standard Cell Library Analysis for Improved Defect Modeling

A comprehensive diagnosis methodology for characterizing logic-behavior of integrated circuit failures

Generalized sensitization using fault tuples