There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Micromachining and micro-electromechanical system (MEMS) technologies can be used to produce complex structures, devices and systems on the scale of micrometers. Initially micromachining techniques were borrowed directly from the integrated circuit (IC) industry, but now many unique MEMS-specific micromachining processes are being developed. In MEMS, a wide variety of transduction mechanisms can be used to convert real-world signals from one form of energy to another, thereby enabling many different microsensors, microactuators and microsystems. Despite only partial standardization and a maturing MEMS CAD technology foundation, complex and sophisticated MEMS are being produced. The integration of ICs with MEMS can improve performance, but at the price of higher development costs, greater complexity and a longer development time. A growing appreciation for the potential impact of MEMS has prompted many efforts to commercialize a wide variety of novel MEMS products. In addition, MEMS are well suited for the needs of space exploration and thus will play an increasingly large role in future missions to the space station, Mars and beyond. (Some figures in this article are in colour only in the electronic version)

https://iopscience.iop.org/article/10.1088/0964-1726/10/6/301/pdf

Microelectromechanical systems (MEMS):fabrication, design and applications

Testing a non-digital integrated system against all of its specifications can be quite expensive due to the elaborate test application and measurement setup required We propose to eliminate redundant tests by employing /spl epsi/-SVM based statistical learning The application of the proposed methodology to an operational amplifier and a MEMS accelerometer reveal that redundant tests can be statistically identified from a complete set of specification-based tests, with negligible error Specifically, after eliminating five of eleven specification-based tests for an operational amplifier, the defect escape and yield loss is small at 06% and 09%, respectively For the accelerometer, defect escape of 02% and yield loss of 01% occurs when the hot and cold tests are eliminated For the accelerometer, this level of compaction would reduce test cost by more than half

https://hal.archives-ouvertes.fr/hal-00181510/document

Specification test compaction for analog circuits and MEMS [accelerometer and opamp examples]

Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more difficult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself At the same time, key diagnostic tasks that include defect localization are still solved using primitive models of the IC's defects This paper explores the use of "fault tuples" in diagnosis Fault tuples can accurately mimic the complex misbehavior of DSM ICs at the logic level, enabling practical diagnosis of large circuits Initial assessment of the use of fault tuples in diagnosis is performed based on a case study involving one specific category of polysilicon spot defects Obtained results indicate that fault tuples may enhance diagnosis significantly

Fault tuples in diagnosis of deep-submicron circuits

Decision-makers typically make test tradeoffs using models that mainly represent direct costs such as test generation time and tester use. Analyzing a test strategy's impact on other significant factors such as test quality and yield learning requires an understanding of the dynamic nature of the interdomain dependencies of test, manufacturing, and design. Our research centers on modeling the tradeoffs between these domains. To answer the DFT question, we developed the Carnegie Mellon University Test Cost Model, a DFT cost-benefit model, derived inputs to the model for various IC cases with different assumptions about volume, yield, chip size, test attributes, and so forth; and studied DFT's impact on these cases. We used the model to determine the domains for which DFT is beneficial and for which DFT should not be used. The model is a composite of simple cause-and-effect relationships derived from published research. It incorporates many factors affecting test cost, but we don't consider it a complete model. Our purpose is to illustrate the necessity of using such models in assessing the effectiveness of various test strategies.

Modeling the economics of testing: a DFT perspective

Application-specific integrated circuit (ASIC) implementations for Deep Neural Networks (DNNs) have been adopted in many systems because of their higher classification speed. However, although they may be characterized by better accuracy, larger DNNs require significant energy and area, thereby limiting their wide adoption. The energy consumption of DNNs is driven by both memory accesses and computation. Binarized Neural Networks (BNNs), as a trade-off between accuracy and energy consumption, can achieve great energy reduction, and have good accuracy for large DNNs due to its regularization effect. However, BNNs show poor accuracy when a smaller DNN configuration is adopted. In this paper, we propose a new DNN model, LightNN, which replaces the multiplications to one shift or a constrained number of shifts and adds. For a fixed DNN configuration, LightNNs have better accuracy at a slight energy increase than BNNs, yet are more energy efficient with only slightly less accuracy than conventional DNNs. Therefore, LightNNs provide more options for hardware designers to make trade-offs between accuracy and energy. Moreover, for large DNN configurations, LightNNs have a regularization effect, making them better in accuracy than conventional DNNs. These conclusions are verified by experiment using the MNIST and CIFAR-10 datasets for different DNN configurations.

https://dl.acm.org/doi/pdf/10.1145/3060403.3060465

LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks

A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit module, independent of the design level. We describe the IP fault model and provide a method for analyzing IP faults using standard single stuck-line- (SSL-) based fault simulators and test generation tools. The method is used to generate test sets that target the IP faults of the ISCAS85 benchmark circuits and a carry-lookahead adder. Improved IP fault coverage for the benchmarks and the adder is obtained by adding a small number of test patterns to tests that target only SSL faults. We also conducted fault simulation experiments that show IP test patterns are effective in detecting nontargeted faults such as bridging and transistor stuck-on faults. Finally, we discuss the notion of IP redundancy and show how large amounts of this redundancy exist in the benchmarks and in SSL-irredundant adder circuits.

R.D. Blanton

Papers

Specification test compaction for analog circuits and MEMS [accelerometer and opamp examples]

Fault tuples in diagnosis of deep-submicron circuits

Modeling the economics of testing: a DFT perspective

LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks

On the properties of the input pattern fault model