There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Micromachining and micro-electromechanical system (MEMS) technologies can be used to produce complex structures, devices and systems on the scale of micrometers. Initially micromachining techniques were borrowed directly from the integrated circuit (IC) industry, but now many unique MEMS-specific micromachining processes are being developed. In MEMS, a wide variety of transduction mechanisms can be used to convert real-world signals from one form of energy to another, thereby enabling many different microsensors, microactuators and microsystems. Despite only partial standardization and a maturing MEMS CAD technology foundation, complex and sophisticated MEMS are being produced. The integration of ICs with MEMS can improve performance, but at the price of higher development costs, greater complexity and a longer development time. A growing appreciation for the potential impact of MEMS has prompted many efforts to commercialize a wide variety of novel MEMS products. In addition, MEMS are well suited for the needs of space exploration and thus will play an increasingly large role in future missions to the space station, Mars and beyond. (Some figures in this article are in colour only in the electronic version)

https://iopscience.iop.org/article/10.1088/0964-1726/10/6/301/pdf

Microelectromechanical systems (MEMS):fabrication, design and applications

Recent research has focused on Deep Neural Networks (DNNs) implemented directly in hardware. However, larger DNNs require significant energy and area, thereby limiting their wide adoption. We propose a novel DNN quantization technique and a corresponding hardware solution, CompactNet that optimizes the use of hardware resources even further, through dynamic allocation of memory for each parameter. Experimental results for the MNIST and CIFAR-10 datasets, show that CompactNet reduces the memory requirement by over 80%, the energy requirement by 12-fold, and the area requirement by 7-fold, when compared to the conventional DNN. This is achieved with minimal degradation to the classification accuracy. We demonstrate that, CompactNet provides pareto-optimal designs to make trade-offs between accuracy and resource requirement. The applications of CompactNet can be extended to datasets like ImageNet, and into models like MobileNet.

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation

In test compaction, the objective is to reduce cost of testing an integrated system by applying a subset of its specification-based tests. One approach for accomplishing this objective is to statistically learn a correlation function for the tests eliminated from a collection of systems that are fully tested (i.e., training data). Accuracy of this correlation function may degrade over the life span of an integrated system however. We describe an adaptive scheme that (1) uses stratified sampling to check the accuracy of a correlation function at various time instances and (2) re-learns a function when its accuracy dips below some tolerable threshold. This methodology is applied to test data from two in-production integrated systems, namely, an accelerometer and a phase-locked loop. Experiments that use over 200,000 real chips demonstrate that the difference between actual function accuracy and its estimate using stratified sampling is smaller than 2%. Moreover, our adaptive re-learning is able to improve the accuracy for one out of three accelerometer and one out of three PLL sampling instances where the function accuracy was unacceptable.

Maintaining Accuracy of Test Compaction through Adaptive Re-learning

Fast and efficient analysis of test chips is crucial for effective yield learning. Prior work proposed the Carnegie-Mellon logic characterization vehicle (CM-LCV) as an improved test chip for yield learning. The highly regular nature of the CM-LCV test chip is particularly appealing for BIST; the current work describes a BIST scheme that achieves 100% input-pattern fault coverage with an 86.9% reduction in test time for a reference design. Furthermore, all of these properties are achieved with a minimal hardware overhead.

Efficient built-in self test of regular logic characterization vehicles

Stringent quality requirements for integrated, heterogeneous systems have led designers and test engineers to mandate large sets of tests to be applied to these systems, which, in turn, have resulted in increased test cost However, many of these tests are unnecessary (ie, redundant), since their outcomes can be reliably predicted using results from other applied tests A methodology for identifying the redundant tests of an integrated, heterogeneous system that has only binary pass-fail test data is described This methodology uses decision trees, Boolean minimization, and satisfiability as core components Feasibility is empirically demonstrated using test data from two commercially fabricated systems, namely, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL) Our analysis of test data from > 38,000 HSS and > 22,000 PLL circuits show that 14 out of 40 HSS tests and 11 out of 36 PLL tests are redundant

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis

Design for manufacturability rule evaluation using manufactured silicon (DREAMS) is a comprehensive methodology for evaluating the yield-preserving capabilities of a set of design for manufacturability (DFM) rules using the results of logic diagnosis performed on failed ICs. DREAMS is an improvement over prior art in that the distribution of rule violations over the diagnosis candidates and the entire design are taken into account along with the nature of the failure (e.g., bridge versus open) to appropriately weight the rules. Silicon and simulation results demonstrate the efficacy of the DREAMS methodology. Specifically, virtual data is used to demonstrate that the DFM rule most responsible for failure can be reliably identified even in light of the ambiguity inherent to a nonideal diagnostic resolution, and a corresponding rule-violation distribution that is counter-intuitive. We also show that the combination of physically aware diagnosis and the nature of the violated DFM rule can be used together to improve rule evaluation even further. Application of DREAMS to the diagnostic results from an in-production chip provides valuable insight in how specific DFM rules improve yield (or not) for a given design manufactured in particular facility. Finally, we also demonstrate that a significant artifact of DREAMS is a dramatic improvement in diagnostic resolution. This means that in addition to identifying the most ineffective DFM rule(s), validation of that outcome via physical failure analysis of failed chips can be eased due to the corresponding improvement in diagnostic resolution.

R.D. Blanton

Papers

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation

Maintaining Accuracy of Test Compaction through Adaptive Re-learning

Efficient built-in self test of regular logic characterization vehicles

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis

DFM Evaluation Using IC Diagnosis Data