There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Micromachining and micro-electromechanical system (MEMS) technologies can be used to produce complex structures, devices and systems on the scale of micrometers. Initially micromachining techniques were borrowed directly from the integrated circuit (IC) industry, but now many unique MEMS-specific micromachining processes are being developed. In MEMS, a wide variety of transduction mechanisms can be used to convert real-world signals from one form of energy to another, thereby enabling many different microsensors, microactuators and microsystems. Despite only partial standardization and a maturing MEMS CAD technology foundation, complex and sophisticated MEMS are being produced. The integration of ICs with MEMS can improve performance, but at the price of higher development costs, greater complexity and a longer development time. A growing appreciation for the potential impact of MEMS has prompted many efforts to commercialize a wide variety of novel MEMS products. In addition, MEMS are well suited for the needs of space exploration and thus will play an increasingly large role in future missions to the space station, Mars and beyond. (Some figures in this article are in colour only in the electronic version)

https://iopscience.iop.org/article/10.1088/0964-1726/10/6/301/pdf

Microelectromechanical systems (MEMS):fabrication, design and applications

To reduce healthcare cost while simultaneously delivering high-quality health services, developing new portable and/or implantable biomedical devices is of great importance for both health monitoring and clinical treatment. In this paper, we describe a radically new design framework for ultra-low-power biomedical circuit design and optimization. The proposed framework seamlessly integrates data processing algorithms and their customized ASIC implementations for co-optimization. The efficacy of the proposed framework is demonstrated by a case study of brain computer interfaces (BCIs).

/pdf/ultra-low-power-biomedical-circuit-design-and-optimization-4zuezh11ch.pdf

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares

To ensure robustness of integrated systems, the TRAnsition-X (TRAX) fault model has been used with on-chip test and diagnosis hardware, utilizing fault dictionaries for diagnosis. Generating a fault dictionary requires fault simulation with no fault dropping, requiring extensive computational resources. This paper presents the design and implementation of an efficient fault simulator for the TRAX fault model, designed to run on a graphics processing unit (GPU). The inherent parallelism of the fault simulation problem maps well to the large number of concurrent threads supported by a modern GPU, and a GPU can be used to accelerate the construction of a fault dictionary. Our approach employs both pattern-parallel and fault-parallel algorithms in the GPU kernel implementations. Experiments involving various circuits, including the OpenSPARC T2 processor, demonstrate a mean speed-up of nearly 8x.

Fault simulation acceleration for TRAX dictionary construction using GPUs

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. In this paper, we address the charge sharing noise issue. Specifically, we develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests were validated using Hspice simulations on industrial circuits and it was also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Testing of dynamic logic circuits based on charge sharing

This paper provides an overview of high-aspect-ratio CMOS micromachining, focusing on materials characterization, reliability, and fault analysis. Composite microstrutural beam widths and gaps down to 1.2 micrometers are etched out of conventional CMOS dielectric, aluminum, and gate-polysilicon thin films using post-CMOS dry etching for both structural sidewall definition and for release from the substrate. Differences in stress between the multiple metal and dielectric layers cause vertical stress gradients and curl, while misalignment between layers causes lateral stress gradients and curl. Cracking is induced in a resonant fatigue structures at 620 MPa of repetitive stress after over 50 million cycles. Beams have withstood over 1.3 billion cycles at 124 MPa stress levels induced by electrostatic actuation. Failures due to process defects are classified according to the geometrical features of the defective structures. Relative probability of occurrence of each defect type is extracted from the process simulation results.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Characterization and reliability of CMOS microstructures

Virtual metrology is an important tool for industrial automation. To accurately build regression models for virtual metrology, we consider semi-supervised learning where labeled data are expensive to collect, but unlabeled data are abundant. In such a scenario, due to the scarcity of labeled data, traditional single-view learning methods face the risk of overfitting. To address the overfitting issue, we develop a Partial Co-training framework, which is an extension of the original co-training approach by means of an undirected probabilistic graphical model. Unlike other co-training techniques, this model creates a partial view by shrinking the original feature space, and makes use of this partial-view to provide guidance information for improving the complete-view model. Our approach is validated with data from two manufacturing applications. The results indicate that a consistent and robust estimation is achievable with very limited labeled data.

R.D. Blanton

Papers

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares

Fault simulation acceleration for TRAX dictionary construction using GPUs

Testing of dynamic logic circuits based on charge sharing

Characterization and reliability of CMOS microstructures

Partial co-training for virtual metrology