There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

(1991). Applied Linear Regression Models. Journal of Quality Technology: Vol. 23, No. 1, pp. 76-77.

Applied Linear Regression Models

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

Micromachining and micro-electromechanical system (MEMS) technologies can be used to produce complex structures, devices and systems on the scale of micrometers. Initially micromachining techniques were borrowed directly from the integrated circuit (IC) industry, but now many unique MEMS-specific micromachining processes are being developed. In MEMS, a wide variety of transduction mechanisms can be used to convert real-world signals from one form of energy to another, thereby enabling many different microsensors, microactuators and microsystems. Despite only partial standardization and a maturing MEMS CAD technology foundation, complex and sophisticated MEMS are being produced. The integration of ICs with MEMS can improve performance, but at the price of higher development costs, greater complexity and a longer development time. A growing appreciation for the potential impact of MEMS has prompted many efforts to commercialize a wide variety of novel MEMS products. In addition, MEMS are well suited for the needs of space exploration and thus will play an increasingly large role in future missions to the space station, Mars and beyond. (Some figures in this article are in colour only in the electronic version)

https://iopscience.iop.org/article/10.1088/0964-1726/10/6/301/pdf

Microelectromechanical systems (MEMS):fabrication, design and applications

The classical single stuck-line (SSL) fault model has been the most commonly used fault model in manufacturing test of digital circuit systems. However, as we push towards newer and more advanced technologies, the SSL fault model is proving to be inadequate due to the growing number of defect types going undetected by the tests generated for SSL faults. Although, several fault types like the bridging fault, transition fault, path delay fault, etc. have been introduced to alleviate the problem of inaccurate modeling of defect behavior, there seems to be no permanent solution in sight. No single fault model seems to be capable of modeling all existing and emerging misbehaviors. The problem of manufacturing reliable and working digital integrated circuits is further compounded by the non-availability of test analysis tools to perform manufacturing test analysis of new defect types. 
An ideal solution to the above mentioned problems is a fault modeling mechanism that is general enough to allow description of the behavior of any type of defect. In this dissertation, we examine the capabilities of a novel fault representation mechanism based on fault tuples as a generalized fault modeling mechanism. A fault tuple is a 3-element tuple f = (l, v, t), where v is the value desired on signal line l during the time-frame described by element t. The syntax and semantics of fault tuples are described in this dissertation. We show how combinations of fault tuples are used to represent the logic-level behavior of defects. 
The implementation issues of test analysis tools based on generalized fault modeling mechanism are addressed by describing the implementation details of FATSIM, a fault simulation system based on fault tuples. FATSIM is an event-driven, gate-level, synchronous sequential fault simulator capable of simulating the properties of fault tuple based macrofaults. The manufacturing test tasks of (a) fault grading, (b) generating fault dictionaries, and (c) fault ordering for test generation are used to demonstrate the capabilities of fault tuples and test analysis tools based on fault tuples.

Fault tuples: theory and applications

Analysis, manipulation, and generation of Boolean circuits is fundamental to many aspects of digital hardware design, cryptography, constraint solving, and other areas. Highly optimized software for processing Boolean circuits exists. Unfortunately it generally is proprietary, with expensive license fees. Furthermore, these options suffer from poor documentation, are closed source, and typically rely on Tool control language (Tcl). While simple, Tcl is slow, has limited libraries and supporting community, and is unnecessarily verbose. These reasons motivate the development of our open source solution. While this software will directly benefit our lab as a research platform, it certainly has application in other environments such as the classroom.

/pdf/circuitgraph-a-python-package-for-boolean-circuits-4sa2phvy82.pdf

CircuitGraph: A Python package for Boolean circuits

At substantial cost, conventional methods for evaluating test quality apply a specially-generated test set to a large population of manufactured chips. In contrast, a new time-efficient framework for evaluating test quality (FETQ) that uses tester data from normal production has been developed and validated. FETQ estimates the quality of both static and adaptive test metrics, where the latter guides test using the results of statistical data analysis. FETQ is innovative since instead of evaluating a single measure of effectiveness (e.g., number of unique defects detected), it provides a confidence interval of effectiveness based on the analysis of a collection of test sets. FETQ is demonstrated by measuring the chip-detection capability of several static and adaptive test metrics using tester data from actual ICs.

Statistical defect-detection analysis of test sets using readily-available tester data

The testability of a class of regular circuits called divergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders and demultiplexers. We prove that uncontrolled divergent trees are testable with a fixed number of test patterns (C-testable) if and only if the module function is surjective. Testable controlled trees are also surjective but require sensitizing vectors for error propagation. We derive the conditions for testing controlled divergent trees with a test set whose size is proportional to the number of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also derive conditions for a controlled divergent tree to be C-testable. Typical decoders/demultiplexers are shown to only partially satisfy L- and C-testability conditions but a design modification that ensures L-testability is demonstrated.

/pdf/testability-properties-of-divergent-trees-59zz3snu2u.pdf

Testability Properties of Divergent Trees

Any type of engineered design requires metrics for trading off both desirable and undesirable properties. For integrated circuits, typical properties include circuit size, performance, power, etc., where for example, performance is a desirable property and power consumption is not. Security metrics, on the other hand, are extremely difficult to develop because there are active adversaries that intend to compromise the protected circuitry. This implies metric values may not be static quantities, but instead are measures that degrade depending on attack effectiveness. In order to deal with this dynamic aspect of a security metric, a general attack model is proposed that enables the effectiveness of various security approaches to be directly compared in the context of an attack. Here, we describe, define and demonstrate that the metrics presented are both meaningful and measurable.

R.D. Blanton

Papers

Fault tuples: theory and applications

CircuitGraph: A Python package for Boolean circuits

Statistical defect-detection analysis of test sets using readily-available tester data

Testability Properties of Divergent Trees

Secuirty Metrics for Logic Circuits