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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 μm CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 μA/V to 165 μA/V) and a total harmonic distortion of −67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

Low-voltage tunable pseudo-differential transconductor with high linearity

Emerging applications in various fields, such as Ambient Intelligence scenarios or remote biomedical monitoring, currently demand wireless sensor networks with transceivers having extremely low power consumption requirements. This is a key issue in order to decrease battery weight and size and to increase the lifetime of the battery, which usually in these sensing nodes is not replaceable. To achieve these strict power requirements, several solutions have been proposed at various layers. At the physical layer, savings in power consumption are achieved by lowvoltage operation and optimized power-to-performance ratio. Supply voltages of 1V (or less) are anyway mandatory in modern deep submicron technologies to operate reliably due to the extremely thin oxide. Furthermore reduction of the supply voltage (even of not required) strongly reduces power consumption in digital circuits since it scales with supply voltage. Although this is not so simple in analog circuits, they should operate at the same supply voltage than the digital part in mixed-mode systems to avoid the complexity involved in generating various supply voltages. The canonic way of designing analog circuits consist in using high-gain amplifiers with passive components in negative feedback loops, both in continuous-time or discrete-time form. Sometimes amplifiers are operated in open loop (e.g. Gm-C filters, some VGAs, etc.), and in this case a large linear range is required for the amplifier at the expense of gain. In any case, amplifiers play a key role in analog design, and their power consumption directly impacts that of the overall analog system. Such amplifiers usually take the form of Operational Transconductance Amplifiers (OTAs) with high output resistance, typically driving capacitive loads, or operational amplifiers with low output resistance able to drive low resistive loads. Besides low-voltage and power-efficient operation, these amplifiers should feature a fast settling response, not limited by slew rate. Conciliating all these requirements is difficult with conventional class A topologies, since the bias current limits the maximum output current. Hence a trade-off between slew rate and power consumption do exists [1]. To overcome this issue, class AB topologies are often employed. These circuits provide well-controlled quiescent currents, which can be made very low in order to reduce drastically the static power dissipation. However, they automatically boost dynamic currents when a large differential input signal is applied, yielding maximum current levels well above the quiescent currents. Several class AB amplifiers have been proposed. Most of them are based on adaptive biasing techniques, by including extra circuitry that increases quiescent currents (e.g. by increasing tail currents in differential stages). However, often the extra circuits included increase both power consumption and silicon area, and add significant parasitic capacitance to the internal nodes. Also positive feedback is often employed to get boosting of dynamic currents, which makes difficult to guarantee stability considering process and temperature variations. In this work we illustrate the use of new circuit design techniques to achieve low-voltage class AB amplifiers that combine

Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits

In this paper a new compact CMOS class AB buffer is presented Its simple implementation relies on the use of the Flipped Voltage Follower (FVF) Simulation results from a 035 /spl mu/m CMOS technology are presented that prove the operating principle under low-power conditions This buffer can also find application in testing of analog CMOS VLSI circuits, as the input capacitance can be very low without diminishing its output drive capability

A new compact low-power high slew rate class AB CMOS buffer

A new very compact and highly linear CMOS OTA, with very wide gain tuning range, is presented. It uses a fixed gain linear V-I converter input stage and electronically programmable current mirrors working in triode which are very compact and continuously adjustable. Programmability is achieved by tuning VDS of the mirroring transistors. The OTA input range and bandwidth is approximately independent of gain adjustment. Simulation results in 0.5/spl mu/m CMOS technology verify the characteristics of the proposed OTA with distortion less than 0.5% over the entire tuning range.

Wide gm adjustment range highly linear OTA with programmable mirrors operating in triode mode

In this paper, a low-power rail-to-rail CMOS analog buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, hence is very suitable for applications with large capacitive loads. The buffer has been designed in a 0.35-/spl mu/m CMOS technology to operate with a /spl plusmn/1.5 V dual supply. Simulated results are provided in order to demonstrate the proper operation of the proposed circuit. A rail-to-rail signal swing is achieved and a THD lower than -44 dB is obtained for a 2.4-V/sub pp/ 100-kHz input sinewave signal, whereas the input capacitance is lower than 32 fF.

Ramon G. Carvajal

Papers

Low-voltage tunable pseudo-differential transconductor with high linearity

Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits

A new compact low-power high slew rate class AB CMOS buffer

Wide gm adjustment range highly linear OTA with programmable mirrors operating in triode mode

Class-AB rail-to-rail CMOS analog buffer