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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

New low-voltage two stage fully differential class AB/AB op-amp architectures with high slew rate are introduced. The proposed circuits are very compact. The output stage does not require a quiescent current control circuit. Simulations are shown verifying high slew rate and rail-to-rail operation with a single supply voltage of 1.5 V and 0.5 /spl mu/m CMOS technology with threshold voltages close to 1 V. The proposed architectures can operate with sub-volt supplies and rail-to-rail output swing in 0.25 /spl mu/m and 0.18 /spl mu/m CMOS technologies.

Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures

A high-performance rail-to-rail sample and hold circuit is presented. It is based on a class AB fully differential rail-to-rail differential difference amplifier. Experimental results of a test chip in 0.5 mum CMOS technology show that it has SFDR = 69.5 dB with plusmn 1.25 V supplies, 2 MHz clock and 2V pp , 200 kHz input signals.

Rail-to-rail fully differential sample and hold based on differential difference amplifier

A tunable highly linear CMOS transconductor with 80dB of SFDR

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW).

Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach

This paper presents a new CMOS transconductor amplifier able to achieve 90dB of SFDR. It is based in the creation of low impedance nodes using local feedback to drive a degeneration resistor. Then, the current generated at the resistor is delivered directly to the output using source coupled pairs. The proposed transconductor does not rely on current mirrors or in cancellation of nonlinear terms, thus improving significantly the linearity and the robustness against mismatch. Simulation results are provided that show THD of 91 dB and an IM3 of 81 dB at 10MHz with 2Vpp differential input-output signal.

Ramon G. Carvajal

Papers

Power efficient fully differential low-voltage two stage class AB/AB op-amp architectures

Rail-to-rail fully differential sample and hold based on differential difference amplifier

A tunable highly linear CMOS transconductor with 80dB of SFDR

Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach

A CMOS transconductor with 90 dB SFDR and low sensitivity to mismatch