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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

A comprehensive analysis of tunable transconductor topologies based on passive resistors is presented. Based on this analysis, a new CMOS transconductor is designed, which features high linearity, simplicity, and robustness against geometric and parametric mismatches. A novel tuning technique using just a MOS transistor in the triode region allows the adjustment of the transconductance in a wide range without affecting the voltage-to-current conversion core. Measurement results of the transconductor fabricated in a 0.5- m CMOS technology confirm the high linearity predicted. As an application, a third-order Gm-C tunable low-pass filter fabricated in the same technology is presented. The measured third-order intermodulation distortion of the filter for a single 5-V supply and a 2-V two-tone input signal centered at 10 MHz is 78 dB. Index Terms—Analog CMOS circuits, continuous-time filters, Gm-Cfilters,harmonicdistortion,transconductors,tunablefilters.

Highly Linear Tunable CMOS - Low-Pass Filter

Two new class AB output stages for CMOS op-amps are proposed with accurate quiescent current control. The second proposed stage also provides accurate control of the minimum current through the output transistors. The proposed stages can be operated with a supply voltage close to a transistor threshold voltage. A dynamic biasing scheme allows them to operate in a wide range of supply voltages. Using these stages two opamps have been designed using a 0.8 μm CMOS technology. Experimental results show a unity gain frequency of 15 MHz with 290 μA of quiescent current and a 10 pF load, using a 1.5 V single voltage supply.

Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

A two-stage (Miller) operational amplifier (opamp) with both class AB input and output stages is introduced. It has a well-controlled quiescent current and generates dynamic output currents of up to a factor 45 times larger than the quiescent current. It uses very compact circuitry with small static power consumption in order to achieve class AB-AB operation and can operate with a low supply voltage. Experimental results of a test chip fabricated using 0.18 μm CMOS technology and simulations in 130, 90, 65 and 45 nm verify the proposed circuit.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/el.2014.4064

Free class AB–AB Miller opamp with high current enhancement

A scheme for low voltage rail-to-rail operation with improved common mode rejection ratio is introduced. It can operate with single supply voltages close to a transistor's threshold voltage and it is very compact and power efficient. It is based on a differential amplifier with floating gate input transistors featuring dynamical adjustment of a floating gate biasing voltage. This reduces significantly common mode voltage variations at the input terminals of the differential pair. The implementation of single ended two stage class AB operational amplifiers based on this scheme is discussed. Experimental results of a test chip in 0.5 mum CMOS technology that validates the proposed scheme are presented.

Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range

A low-voltage and low-power front-end for miniaturized, wearable EEG systems is presented. The instrumentation amplifier, which removes the electrode drift and conditions the signal for a 10-bit A/D converter, combines a chopping strategy with quasi-FGMOS (QFG) transistors to minimize low frequency noise whilst enabling operation at 1 V supply. QFG devices are also key to the A/D converter operating at 1.2 V with 70 dB of SNR and an oversampling ratio of 64. The whole system consumes less than 2 muW at 1.2 V.

/pdf/a-low-voltage-low-power-front-end-for-wearable-eeg-systems-43l99mdv7m.pdf

Ramon G. Carvajal

Papers

Highly Linear Tunable CMOS - Low-Pass Filter

Class AB Output Stages for Low Voltage CMOS Opamps with Accurate Quiescent Current Control by Means of Dynamic Biasing

Free class AB–AB Miller opamp with high current enhancement

Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range

A Low-Voltage Low-Power Front-End for Wearable EEG Systems