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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

This paper proposes two new offset compensation techniques based on unbalanced polarization. They are based on the use of transistors operating in subthreshold to sense the DC offset and to use this value to generate unbalanced bias currents. These strategies do not degrade the frequency response and have smaller cost in area, power consumption and complexity than other offset compensation techniques. As a proof of concept, two low-voltage, current-mode multipliers and dividers using these strategies and designed in a 0.5 /spl mu/m CMOS process are presented.

Offset compensation using unbalanced polarization

A compact implementation of a single transistor tail current source with very high output impedance (>40 MOmega) and low-voltage requirements is introduced. The tail transistor can operate with less than a drain-source saturation voltage and allows implementation of low-voltage differential pairs with wide common-mode input range and very high common-mode rejection ratio. Simulation and experimental results are shown that validate the proposed circuit.

Single Transistor High-Impedance Tail Current Source With Extended Common-Mode Input Range and Reduced Supply Requirements

Two schemes for low-voltage CMOS op-amp operation with large input signal swing and constant gm are presented. One of the schemes is based on the use of capacitive dividers with multiple-input floating-gate transistors and the second on a novel concept denoted dynamic battery biasing that uses a battery to keep the op-amp input terminals close to one of the supply rails. Simulations are presented that verify the schemes operating with a 1.2 V single supply, 1 V input output swing and 38 MHz op-amp gain-bandwidth product, 130 /spl mu/W power dissipation with a 10 pF load while using 300/spl times/300 /spl mu/m/sup 2/ silicon area. These results are obtained for 0.85 V transistor's threshold voltages. Experimental results are shown that verify the correct functionality of both approaches.

Low voltage CMOS op-amps for a supply close to a transistor's threshold voltage

A family of low-voltage power-efficient class AB CMOS operational transconductance amplifiers (OTAs) is described. It is based on the combination of adaptive biasing techniques and resistive local common-mode feedback (LCMFB), which provides increased dynamic current boosting and gain-bandwidth product (GBW). The different classes of AB OTA topologies presented result from the combination of various adaptive biasing schemes and LCMFB. A 0.5-/spl mu/m CMOS implementation of three different OTAs shows enhancement factors of slew-rate and GBW up to 280 and 3.6, respectively, for an 80-pF load, compared to a conventional class A OTA with the same quiescent currents and supply voltage. The overhead in area, noise, and static power consumption, is minimal.

Power-efficient super class AB OTAs

A micropower single-stage folded cascode amplifier able to drive a wide range of capacitive loads is presented. It features class AB operation and includes power-efficient adaptive biasing techniques, which provide enhanced dynamic output current boosting and gain-bandwidth product (GBW). Phase lead compensation is used to improve phase margin and settling performance for low capacitive loads. Measurement results for a 0.5 μm CMOS process show a FoM of 5540 MHz pF/mA, the highest one reported to date for a folded cascode amplifier to the authors' knowledge.

/pdf/folded-cascode-ota-with-5540-mhzpf-ma-fom-2gsghljczf.pdf

Ramon G. Carvajal

Papers

Offset compensation using unbalanced polarization

Single Transistor High-Impedance Tail Current Source With Extended Common-Mode Input Range and Reduced Supply Requirements

Low voltage CMOS op-amps for a supply close to a transistor's threshold voltage

Power-efficient super class AB OTAs

Folded Cascode OTA with 5540 MHzpF/mA FoM