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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

Power and area efficient continuous time ΣΔ modulator based on local feedback

A novel tunable third order low-pass Gm-C filter is introduced. Programmable transconductors operating in class AB have been used for its implementation hence featuring low quiescent power consumption. The operation in class AB is achieved using quasi-floating gate transistors. This filter is suitable for channel filtering of highly integrated, ultra low power wireless receivers e.g. for Bluetooth and Zigbee. Measurement results for a test chip prototype in a low-cost 0.5μm standard CMOS process are presented.

Tunable class AB CMOS Gm-C channel filter for a bluetooth zero-IF receiver

It is shown that utilization of local common mode feedback in one-stage operational amplifiers can provide significant improvement in the slew rate and gain bandwidth with essentially the same silicon area and static power dissipation. A comparison of one stage CMOS and BiCMOS single ended and fully differential architectures with and without local common mode feedback is presented. Experimental and simulation results are shown that verify the expected performance improvements.

New architectures of class AB CMOS and BiCMOS operational amplifiers with local common mode feedback

Demodulator (1) for detecting digitally phase or frequency modulated signals comprising an in-phase component (i(t)) and a quadrature component (q(t)), said demodulator comprising: a linear combiner (3) for generating a plurality of 2N linear combinations of said in-phase component and said quadrature component; a plurality of amplitude limiters (40-1, 40-2, 40-3, 40-4, 40-5, 40-6, 40-7, 40-8) at the output of each of said linear combinations for providing a digital code (C0 C1 C2 C3 C4 C5 C6 C7) which represents a phase quantization sector of said linear combinations; a stage (50, 50a, 50b) for providing a decoded symbol (Data0 Data1 Data2 Data3) having M=log 2 (4N) bits, for comparing (53a, 53b) said decoded symbol (Data0 Data1 Data2 Data3) with a delayed symbol (Data0' Data1' Data2' Data3') and for providing a symbol (out0 out1 out2 out3) resulting from said comparison; a flip-flop (9) placed at the output of said stage (50, 50a, 50b) for selecting a most significant bit (out3) of said provided symbol (out0 out1 out2 out3) resulting from said comparison; the demodulator (1) being characterised in that it further comprises: a post-processing stage (8) located between said stage (50, 50a, 50b) and said flip-flop (9), said post-processing stage (8) being designed for compensating for errors at the output (outFF) of said flip-flop (9).

Ramon G. Carvajal

Papers

Power and area efficient continuous time ΣΔ modulator based on local feedback

Tunable class AB CMOS Gm-C channel filter for a bluetooth zero-IF receiver

New architectures of class AB CMOS and BiCMOS operational amplifiers with local common mode feedback

Demodulator with post-processing circuit for BER improvement