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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

A CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm.

Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

A new class AB output stage for CMOS op-amps is proposed with simple and accurate quiescent current control using floating gate transistors. The proposed stage can be operated with a supply voltage close to a transistor's threshold voltage. Experimental results are provided showing a 15 MHz gain-bandwidth product when it is used as the second stage of an op-amp with 1.5 V supply voltage in a standard 0.8 μm CMOS technology.

Low Voltage Class AB Output Stage for CMOS Op-Amps Using Multiple Input Floating Gate Transistors

A novel class AB second-generation CMOS current conveyor (CCII) is presented. Class AB operation is achieved without increasing supply voltage requirements or power consumption. The circuit also features very low input resistance at terminal X. The CCII has been fabricated in a 0.5-µm CMOS technology. Measurement results using a dual supply voltage of ±1.65V show a THD of −60dB at 120 kHz in current follower configuration, for input and output currents 20 times larger than the bias current. The quiescent power of this configuration is 99 µW and the silicon area is 0.02 mm2.

Micropower class AB CMOS current conveyor based on quasi-floating gate techniques

A low voltage rail to rail highly linear voltage to current conversion technique is presented. This is based on flipped voltage follower regulated cascode mirror. As an example application of this technique, a current mode successive approximation analog-to-digital converter (ADC) architecture is presented. Cadence simulation results of the 8-bit ADC are presented which show that the ADC works in range up to 202 KS/s with a single supply of 1.8 V and 3.21mW static power dissipation in 0.5/spl mu/m CMOS technology.

A low voltage rail to rail V-I conversion scheme for applications in current mode A/D converters

A new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called the "flip voltage follower," have been used in the past for different applications. New circuits using this cell are also proposed here.

Ramon G. Carvajal

Papers

Current-mode CMOS multiplier/divider circuit operating in linear/saturation regions

Low Voltage Class AB Output Stage for CMOS Op-Amps Using Multiple Input Floating Gate Transistors

Micropower class AB CMOS current conveyor based on quasi-floating gate techniques

A low voltage rail to rail V-I conversion scheme for applications in current mode A/D converters

Low-power low-voltage analog electronic circuits using the flipped voltage follower