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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

A new linear tunable CMOS transconductor is presented here. This circuit uses a new low-voltage supercascode transistor to provide a high output resistance. Using a standard 0.8 /spl mu/m CMOS technology simulation results are provided that show the operation of the proposed transconductor with 1.5 V supply voltage featuring less than 0.1% THD for a 10 MHz, 0.6 V peak-to-peak differential input signals. The simulated -3 dB bandwidth is larger than 100 MHz.

A new 1.5V linear transconductor with high output impedance in a large bandwidth

Extra features are added to the conventional CCII in order to extend the use of CCII-based filters to high-performance applications in submicron CMOS technologies. They include continuous programming of current gain and fully balanced low voltage low power operation in moderate inversion region. Measurement results of a biquad fabricated in a 0.5-/spl mu/m CMOS process are included that validate the proposed approach.

Design of high-performance tunable filters based on current conveyors

A very low distortion low-voltage CMOS OTA with very wide g\"m adjustment and input range is presented. It is based on a fixed gain novel highly linear voltage-to-current conversion input stage and uses electronically programmable current mirrors to achieve very wide transconductance gain adjustment range. The OTA input range remains approximately constant with g\"m adjustment. Bandwidth and input signal range can be adjusted independent of g\"m. Simulations results in [email protected] CMOS technology with +/-1V supplies and 1V input range are presented which confirm the characteristics of the proposed structure.

Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion.

A super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date.

1-V 15-μW 130-nm CMOS Super Class AB OTA

A new family of two stage op-amps with broadband open loop response is introduced. These have a significant reduction of the DC open loop gain and maintain a high gain at frequencies as low as 1 Hz. This provides them with low DC offset. The proposed circuits are based on the Quasi-Floating Gate (QFG) technique, using a novel implementation for active loads that provides a very low effective resistance at DC and very-low frequencies without penalizing the high resistance at the pass band gain significantly. Moreover, a wide-band AC coupling structure also based on QFG transistors has been combined with the proposed technique, rejecting both the differential input DC voltage and the offset introduced by the circuit. These features make the proposed op-amps suitable for biological signal processing, where small amplitude signals are commonly affected by large DC offsets. Cadence simulation results employing a 0.5 micrometers technology are provided for validating the proposed circuits.

Ramon G. Carvajal

Papers

A new 1.5V linear transconductor with high output impedance in a large bandwidth

Design of high-performance tunable filters based on current conveyors

Highly Linear Wide Input Range CMOS OTA Architectures Operating in Subthreshold and Strong Inversion.

1-V 15-μW 130-nm CMOS Super Class AB OTA

CMOS op-amps for biomedical applications