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Design Of Analog Cmos Integrated Circuits

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

This paper presents a fully integrated programmable biomedical sensor interface chip dedicated to the processing of various types of biomedical signals. The chip, optimized for high power efficiency, contains a low noise amplifier, a tunable bandpass filter, a programmable gain stage, and a successive approximation register analog-to-digital converter. A novel balanced tunable pseudo-resistor is proposed to achieve low signal distortion and high dynamic range under low voltage operations. A 53 nW, 30 kHz relaxation oscillator is included on-chip for low power consumption and full integration. The design was fabricated in a 0.35 mum standard CMOS process and tested at 1 V supply. The analog front-end has measured frequency response from 4.5 mHz to 292 Hz, programmable gains from 45.6 dB to 60 dB, input referred noise of 2.5 muVrms in the amplifier bandwidth, a noise efficiency factor (NEF) of 3.26, and a low distortion of less than 0.6% with full voltage swing at the ADC input. The system consumes 445 nA in the 31 Hz narrowband mode for heart rate detection and 895 nA in the 292 Hz wideband mode for ECG recording.

A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

In this paper a new basic cell for low-power and/or low-voltage operation is identified. It is shown that different versions of this cell, called "flipped voltage follower", have been used in the past for different applications. New circuits using this cell are also proposed here.

Super Class AB OTAs Based on Low-Power Adaptive Techniques at the Input Stage and the Active Load

A new method to achieve highly linear scaling of differential currents in CMOS technology is presented. It is based on operation in weak or moderate inversion of FGMOS transistors, and features performance improvements over previous proposals aimed to the same goal, like reduced supply voltage requirements, increased power efficiency, and avoidance of bulk effect. Measurement results of a 0.5 mum CMOS technology are presented that verify the proposed approach.

Low-voltage FGMOS-based balanced current scaling in moderate inversion

A CMOS transconductor suitable for very low distortion analog signal processing over a rail-to-rail input range is presented Very low impedance virtual ground nodes obtained by local negative feedback allow a highly linear voltage to current conversion by passive resistors Low mismatch sensitivity is achieved as the current generated in the resistors is not internally replicated Measurement results for a 05/spl mu/m CMOS prototype show a spurious-free dynamic range at 1MHz higher than 70dB for a 6Vpp input and a dual supply of /spl plusmn/15V

A 70dB SFDR CMOS transconductor

A low distortion low-voltage BiCMOS OTA with wide gm adjustment range and constant input range is presented. It is based on a highly linear voltage-to-current converter input stage merged with translinear loops that implement linear electronically programmable current mirrors. Experimental results are provided that confirm the characteristics of the proposed OTA with a single 1.7V supply, 1.2V input range, two decades gain adjustment range, and 0.3% THD.

Low-voltage wide gm adjustable range highly linear BiCMOS OTA

A simple input offset compensation scheme, with reduced sensitivity to charge injection and leakage, is introduced. It stores an amplified version of the offset that is applied during normal operation on the input side through a capacitive divider. Offset compensation takes place in a voltage additive manner in a separate path from the input signal. Experimental results of a test chip are shown that validate the proposed scheme.

Ramon G. Carvajal

Papers

Super Class AB OTAs Based on Low-Power Adaptive Techniques at the Input Stage and the Active Load

Low-voltage FGMOS-based balanced current scaling in moderate inversion

A 70dB SFDR CMOS transconductor

Low-voltage wide gm adjustable range highly linear BiCMOS OTA

Input offset compensation scheme with reduced sensitivity to charge injection and leakage