We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.

/pdf/all-digital-pll-and-transmitter-for-mobile-phones-2mf5fxyzjo.pdf

All-digital PLL and transmitter for mobile phones

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

https://users.ece.utexas.edu/~adnan/comm-08/bluetooth-jssc-04.pdf

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

After being the subject of speculation for many years, a software-defined radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz

The Path to the Software-Defined Radio Receiver

A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS

A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.

A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation

A contactless system is described in which multiple execution environments may be coupled to a near field communication (NFC) controller, wherein each execution environment is configured to communicate with remote readers via the NFC controller using an assigned one of a plurality of communication protocols. During a polling session from a proximate reader, responding to a request command using a requested communication protocol and activating one of the plurality of execution environments assigned to the requested communication protocol to use the NFC controller. An arbitration is performed in response to each polling session such that a same combination of communication protocol and execution environment is not activated for adjacent polling sessions.

Multiple NFC Card Applications in Multiple Execution Environments

A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

A contactless system is described in which energy is scavenged from an electromagnetic field provided by a proximate reader device. An embedded processor and a volatile memory circuit within a near field communication (NFC) controller are operated using the scavenged energy. Parameter data from the proximate reader device may be acquired while conducting a near field communication transaction. A non-volatile memory (NVRAM) server is coupled to the NFC controller and also operates using the scavenged energy. Parameter data may be stored within the NVRAM server by sending a command and the parameter data from the NFC controller to the NVRAM server. At the completion of the transaction, the electromagnet field may be removed and all parameter data stored within the NFC controller will be lost. However, the next time the electromagnetic field is applied, the NFC controller may retrieve the parameters from the NVRAM server by sending a command.

Non-Volatile Memory for Contactless Systems

A novel and useful low power Bluetooth page and inquiry scan mechanism. Efficient and low power page and inquiry scans are performed by measuring the energy received at each frequency and comparing it to a threshold. If the energy sensed is greater than the threshold, normal Bluetooth page or inquiry scans are then performed within the scan window. The energy sensing is done by quickly sweeping the receiver in the radio over all 79 Bluetooth frequencies in less than 68 μs at least 19 times in order to cover at least 1.25 ms thus ensuring capturing any page or inquiry message transmissions. For noisy environments, a mechanism is provided to turn frequency sweeping off until interference is at a low enough level to reduce the number of false positive detections to an acceptable level.

Ran Katz

Papers

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Multiple NFC Card Applications in Multiple Execution Environments

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

Non-Volatile Memory for Contactless Systems

Low power bluetooth page and inquiry scan