Showing papers by "Rao Tummala published in 2020"

A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues

Abstract: Power module packaging technologies have been experiencing extensive changes as the novel silicon carbide (SiC) power devices with superior performance become commercially available. This article presents an overview of power module packaging technologies in this transition, with an emphasis on the challenges that current standard packaging face, requirements that future power module packaging needs to fulfill, and recent advances on packaging technologies. The standard power module structure, which is a widely used current practice to package SiC devices, is reviewed, and the reasons why novel packaging technologies should be developed are described in this article. The packaging challenges associated with high-speed switching, thermal management, high-temperature operation, and high-voltage isolation are explained in detail. Recent advances on technologies, which try to address the limitations of standard packaging, both in packaging elements and package structure are summarized. The trend toward novel soft-switching power converters gave rise to problems regarding package designs of unconventional module configuration. Potential applications areas, such as aerospace applications, introduce low-temperature challenges to SiC packaging. Key issues in these emerging areas are highlighted.

A Review of 5G Front-End Systems Package Integration

Abstract: Increasing data rates, spectrum efficiency and energy efficiency have been driving major advances in the design and hardware integration of RF communication networks. In order to meet the data rate and efficiency metrics, 5G networks have emerged as a follow-on to 4G, and projected to have 100X higher wireless date rates and 100X lower latency than those with current 4G networks. Major challenges arise in the packaging of radio-frequency front-end modules because of the stringent low signal-loss requirements in the millimeter-wave frequency bands, and precision-impedance designs with smaller footprints and thickness. Heterogeneous integration in 3D ultra-thin packages with higher component densities and performance than with the existing 2D packages is needed to realize such 5G systems. This paper reviews the key building blocks of 5G systems and the underlying advances in packaging technologies to realize them.

Broadband and Miniaturized Antenna-in-Package (AiP) Design for 5G Applications

Abstract: A broadband and miniaturized planar Yagi antenna-in-package (AiP) design for the fifth-generation (5G) wireless communication is proposed The monopole taper radiator is adopted for the proposed Yagi antenna design to miniaturize the size, extend the bandwidth, and simplify the feeding network The proposed AiP design is broadband enough to cover all three 5G New Radio bands simultaneously The high-precision high-resolution multilayered glass packaging fabrication process with a new low-loss polymer material coating is adopted to realize the circuit The operation band is from 2425 to 40 GHz and the fractional bandwidth is 49% The overall size for an antenna element is 305 mm × 556 mm, which is equal to 025 $\lambda _0$ × 045 $\lambda _0$ The measured $S_{11}$ is smaller than $-$ 10 dB within the entire band and the gain is larger than 4 dBi A two-by-one array using the proposed element is also demonstrated with a gain higher than 62 dBi within the entire band Compared with previous works, the proposed AiP design can cover all 5G bands with a competitive size Thus, it is suitable to be applied to massive arrays and easily integrated into packages to achieve compact system-in-package applications while resolving numerous current 5G challenges, including millimeter-wave (mm-wave) path loss and transmission loss

Glass-Based IC-Embedded Antenna-Integrated Packages for 28-GHz High-Speed Data Communications

Abstract: Chip-embedded mm-wave antenna-integrated modules are demonstrated, for the first time, on panel-scale ultra-thin glass substrates, for high-speed 5G communication standards in the n257 band (26.5 – 29.5 GHz) defined by 3GPP. Co-packaging of amplifiers, filters, and antennas with minimal package parasitics is the key to realize mm-wave package systems. Parasitics arise from on-package and chip-to-package interconnects. This paper focuses on reduced chip-to-package losses and implementation of filters and antennas with chip-embedding structures in glass substrates. To demonstrate the benefits of glass-panel embedding (GPE) for 5G communications, the interconnect losses are benchmarked with the C4-bump based flip-chip technique. The electrical performance shows that the chip-embedding structure with a glass substrate lead to 3X lower insertion loss from chip to antenna than the flip-chip assembly method with C4 bumps. This reduced chip-to-antenna insertion loss brings about the enhanced efficiency and gain of the patch antennas integrated on top of the glass substrates. The process development and electrical performance are benchmarked with emerging 5G substrate technologies such as fan-out wafer level packaging.

Ultrathin Antenna-Integrated Glass-Based Millimeter-Wave Package With Through-Glass Vias

Abstract: This article presents the design and demonstration of a high-bandwidth antenna-in-package (AiP) module focusing on low-loss interconnects and Yagi–Uda antenna performance fabricated on a 100- $\mu \text{m}$ low coefficient-of-thermal-expansion (CTE) glass for the 28-GHz band. It shows the modeling, design, and characterization of key technology building blocks along with the process development of advanced 3-D glass packages. The building blocks include impedance-matched antenna-to-die signal transitions, Yagi–Uda antenna, and 3-D active–passive integration with backside die assembly on 100- $\mu \text{m}$ glass substrates. The design and stack-up optimization of antenna-integrated millimeter-wave (mm-wave) modules is discussed. Process development to achieve high-density interconnects and precise dimensional control in multilayered thin glass-based packages is also described. The characterization results of the key technology building blocks show an insertion loss of 0.021 dB per through-package via (TPV), leading to the whole-chain loss of less than 1 dB and a return loss lower than 20 dB. The fabricated Yagi–Uda antenna features high repeatability of wide bandwidth due to the process control enabled by glass substrates. The antenna measurements show a bandwidth of 28.2%, which covers the entire 28-GHz fifth-generation (5G) frequency bands (n257, n258, and n261). The flip-chip assembled low-noise amplifier with 80- $\mu \text{m}$ solder balls shows a maximum gain of 20 dB as desired. The performance of the glass-based package integrated antennas is benchmarked to other 5G substrate technologies, such as organic laminates or co-fired ceramic-based substrates.

Package-Integrated, Wideband Power Dividing Networks and Antenna Arrays for 28-GHz 5G New Radio Bands

Abstract: Package-integrated and ultrathin power dividers with footprint smaller than unit $\lambda ~_{0}~^{\mathrm{ 2}}$ at the operating frequency of 28-GHz 5G new radio (NR) n257 and n258 bands are presented for the first time for small-cell applications. These power dividers are also configured as antenna arrays using endfire Yagi–Uda antenna elements. Utilizing minimal matching techniques, two-, three-, and four-element antenna arrays are designed without compromising on the bandwidth of operation or electrical performance. These thin-film power dividers exhibit a cross-sectional height of $147~\mu \text{m}$ and can be implemented in the top metal layer of front-end module packages. Panel-compatible semiadditive patterning (SAP) process is utilized to realize these structures, which yields precise line space dimensions required for millimeter-wave (mm-wave) applications. This results in power dividers with low added insertion loss, low VSWR, and minimal phase difference between output ports. The added insertion loss is 25% less than similar structures reported on integrated fan-out architectures. The antenna arrays exhibit high gain and efficiency. Excellent model-to-hardware correlation is observed with multiple coupons of the same structure. Package-integrated power dividers and antenna arrays based on ultrathin laminated glass substrate represent a major step toward realizing compact mm-wave antenna-in-package for 5G small-cell applications.

Large-body-sized Glass-based Active Interposer for High-Performance Computing

Abstract: This paper presents a next generation glass-based active interposer with 2 micron polymer RDL. Passive 2.5D interposers have become a mainstream solution to address the bandwidth demands of high-performance computing (HPC) applications. However, such passive interposers face challenges in meeting future performance, cost and reliability needs and active interposers have been studied recently as a means of scaling interposer performance. Given the ability to grow CMOS on Silicon more readily, only Silicon has been studied as substrate core for active interposers. However, for large body sizes, Silicon is not cost effective and interconnects tend to be lossy over long distances. Glass has been explored as a passive interposer core previously, and glass-based panel embedding (GPE) solutions have also been developed for fanout applications. This work uses GPE technology to demonstrate a glass-based active interposer substrate with potential for large-body-sized packages. The key challenge, however, in achieving a wiring density of over 250 IO/mm is the surface non-coplanarities associated with cavities in glass substrates. This paper describes the fabrication process for a Glass-based active interposer with dies embedded in glass cavities, and a systematic parametric process optimization to improve the surface planarity to demonstrate 2 micron L/S RDL on die-embedded glass substrates.

Wideband Power/Ground Noise Suppression in Low-Loss Glass Interposers Using a Double-Sided Electromagnetic Bandgap Structure

Abstract: In this article, we propose a double-sided electromagnetic bandgap (DS-EBG) structure for glass interposers (GIs) with low substrate loss to suppress power/ground noise. For the first time, we validated wideband power/ground noise suppression in the GI using the proposed DS-EBG structure based on dispersion analysis and experimental verification. We experimentally verified that the proposed DS-EBG structure achieved the power/ground noise suppression (below −40 dB) between 2.5 and 8.9 GHz in the GI. Derived stopband edges, $f_{L}$ and $f_{U}$ based on the dispersion analysis, and 3-D electromagnetic (EM) simulation showed a good correlation with measurements. The effectiveness of the proposed DS-EBG structure on the power/ground noise suppression is verified by analyzing noise propagation in the power distribution network and coupling to the GI channel. Using the 3-D EM simulation, we verified that the proposed DS-EBG structure suppressed the power/ground noise coupling and improved the eye diagram of the GI channel. Finally, we propose a design methodology to broaden the isolation bandgap or miniaturize the dimensions based on the dispersion analysis.

Low-Loss Impedance-Matched Sub-25-μm Vias in 3-D Millimeter-Wave Packages

Abstract: This article presents, for the first time, low-loss small microvias in build-up layers for the next-generation high-density high-performance fifth-generation (5G) millimeter-wave (mm-wave) antenna-integrated packages. As the operating frequency increases, the signal losses in antenna packages become more critical and need to be mitigated to obtain desired performance in beamforming and massive multi-input multi-output. As electrical wavelengths in mm-wave spectra are short, the signal losses caused by microvias dominate the loss budget. To minimize the signal losses and identify the required microvia diameter in build-up layers, this article first focuses on the modeling of small microvias for impedance matching. Based on the models and simulated characteristic impedance, test vehicles with daisy chains are fabricated in build-up layers on a core package substrate. Ultraviolet (UV) laser is utilized to drill microvias, and targeted microvia diameters are obtained through a semiadditive patterning process. High-frequency measurements are also performed to correlate with the models and simulated results in the 28-GHz band. The characterization results exhibit good model-to-hardware correlation and indicate that small microvias (20 $\mu \text{m}$ ) provide impedance closer to $50~\Omega $ compared with the larger microvias. This matched microvia impedance lowers reflection and insertion loss, resulting in a 10% reduction in the signal losses caused by microvias in the 5G New-Radio n257 band around 28 GHz.

Ultralow-Loss Substrate-Integrated Waveguides in Glass-Based Substrates for Millimeter-Wave Applications

Abstract: This letter, for the first time, presents low-loss substrate-integrated waveguides (SIWs) in fused silica and borosilicate glass and a comparison of their performance with various organic-based low-loss substrates for millimeter-wave applications. Utilizing ring resonators designed for frequencies in the 5G New Radio (NR) n257 band (26.5–29.5 GHz), this letter begins with the determination of the dielectric constant of fused silica to model SIWs. This letter also introduces the designs of SIWs that are fed by conductor-backed coplanar waveguides and discusses the fabrication and measurement results with deembedding analysis. In addition to the excellent correlation between simulations and measurements, the characterization results show more than $2\times $ reduction in the insertion loss compared to those of low-loss organic-based SIWs at the 28-GHz frequency band.

Smaller Microvias for Packaging Interconnects by Picosecond UV Laser With a Nanometer Metal Barrier Layer: A Feasibility Study

Abstract: This study, to the best of authors’ knowledge, is the first to investigate the feasibility of using picosecond UV laser ablation to fabricate ultrasmall microvias scaled down to 3 $\mu \text{m}$ and less with a pitch of 8 $\mu \text{m}$ in a 5- $\mu \text{m}$ Ajinomoto buildup film (ABF). The state-of-the-art microvias are 20 $\mu \text{m}$ in diameter by a nanosecond UV laser and 5 $\mu \text{m}$ in diameter by a picosecond UV laser reported in our previous study, but microvias of less than 2 $\mu \text{m}$ in diameter are needed to meet IO density requirements for today and future’s high-bandwidth packaging and heterogeneous system integration. In this study, we have investigated the impact of laser power, beam sizes, and materials on the via size and explored the feasibility of picosecond UV laser ablation for ultrasmall microvias with an additional layer of 80-nm-thick copper on top of the dielectric as a barrier layer. The power used to fabricate the 5- $\mu \text{m}$ microvias in a 5- $\mu \text{m}$ -thick ABF could open 2- $\mu \text{m}$ holes in the copper barrier layer due to the higher ablation threshold of copper. The drilled copper layer then serves as a mask to produce smaller microvias in the dielectric layer beneath the copper. In this article, fully opened microvias of 3 $\mu \text{m}$ diameter in ABF will be demonstrated. Submicrometer openings in copper are also achieved, which suggests the feasibility to scale down via diameter to submicrometer level.

Heterogeneous Integration of 5G and Millimeter-Wave Diplexers with 3D Glass Substrates

Abstract: Package-integrated implementation of highly- miniaturized diplexers is presented for the first time on ultra-thin laminated glass substrates for millimeter-wave (mm-wave) applications in emerging RF front-end modules (FEM). The diplexers are designed using miniaturized, doubly- terminated bandpass filters which cover the 5G new radio (NR) mm-wave bands: n257, n258 and n260. Two different types of filters: hairpin and edge-coupled are modeled, designed and optimized for this non-contiguous diplexer demonstration. Since diplexer is a three-port device, the considerations for optimum RF performance as well as characterization are included in the modeling phase. From the fabrication standpoint, unlike conventional etching processes, panel-scale semi-additive patterning (SAP) process is utilized to form high-precision, fine-feature redistribution layers (RDL) on ultra-thin glass substrates to accurately realize the aforementioned passive components. These diplexers can be integrated with antennas on the top layer of a multilayered 5G module or they can be utilized as integrated passive devices (IPDs). An appropriately sized ground plane is sufficient to isolate the rest of the system from these diplexers, making them ideal for applications such as heterogeneously-integrated packages. The demonstrated diplexers, comprising of 5G NR band filters, exhibit low insertion loss, high stopband rejection, high selectivity, ease-of-integration in packages as well as small footprint. The simulated response of the fabricated diplexers is in excellent agreement with the measured results.

Design and Demonstration of Single and Coupled Embedded Toroidal Inductors for 48V to 1V Integrated Voltage Regulators

Abstract: High-efficiency High-Voltage Integrated Voltage Regulators (HV-IVR) will allow the next generation of data centers and servers to operate with higher efficiency while delivering more computing power. High-density embedded inductors operating at frequencies over 10 MHz allows the miniaturization of power modules enabling their integration closer to the SoC. However, single stage 48V to 1V IVR present new challenges that are not seen in low voltage converter such as 3.3V or 1.7V to 1V. In this work, a novel expandable interleaved toroidal inductor cell with vias-in-slot thru magnetic sheet is presented. In addition, we present a new metric for magnetic material and inductor technologies to describe their efficiency under different duty cycle conditions. Using the analysis of two available magnetic sheets with permeability 50 and 150 at 10MHz, we present the magnetic properties of a magnetic sheet to obtain 95% of inductor efficiency, an inductance density of 113 nH/mm3 at 10 MHz, a saturation current over 2.5A, and DC resistance around 20 mΩ. These inductor requirements are given by the possible power stage topologies that can be used to achieve 48V to 1V, where some of them use single inductor while others use coupled or tapped inductors. The efficiency conditions for the inductor presented in this work must be matched by the power stage topology, leading to a co-design between power inductor and the power stage topology. In this work we present why the duty cycle must be extended by a factor of 4 in order to obtain a 95% efficiency in the inductor. We provide a process for the fabrication of these inductors. Finally, a test inductor is fabricated that shows an inductance density of 77 nH/mm3 and correlates well with the simulation model. This allows to predict with good accuracy the inductor performance with the proposed inductor design and magnetic sheet properties.

Effect of Solder Paste Volume and Reflow Parameters on Solder Paste Wicking and Joint Shear Strength of Ni–Au-Coated Cu Spheres

Abstract: Ball grid array (BGA) architectures are being widely used in the semiconductor industry in surface mount technology (SMT) applications to satisfy the miniaturization needs of emerging microelectronics systems. However, these architectures are not compatible with socketing applications as the mechanical contact between the gold paddle and the solder sphere leads to undesired reactions, increasing the contact resistance and degrading the reworkability overtime. To address this challenge, surface modification of BGA spheres with multilayered thin-film metallic coatings such as Ni-Au is proposed to maintain a nonreactive noble metal interface when used in a socket. This article focuses on the process of attaching the surface-modified spheres on a package using two solder pastes—Sn57.6Bi0.4Ag (SBA) and Sn3.0Ag0.5Cu (SAC305) with liquidus temperatures of 138 °C and 219 °C, respectively. The challenge of solder paste wicking on the entire surface of the Au-coated sphere was addressed by controlling the volume of the solder paste, and the joint shear strength was optimized by controlling the time above liquidus (TAL) during reflow. A 30–40-s window for TAL was established to achieve a strong solder joint with controlled paste wicking for both solder pastes. The strength of the joint was measured by a single-ball shear test, followed by microstructural analysis to identify the failure modes. Brittle fractures were observed for both solder pastes with an optimum joint shear strength ranging from 55 to 70 MPa for the SBA paste, and 72 to 75 MPa for the SAC305 paste.

Sintered Nanocopper Paste for High-Performance 3D Heterogeneous Package Integration

Abstract: Fifth-generation (5G) communications have been driving major package innovations to enable low-loss interconnects between the integrated circuits (IC) and other system components such as antenna arrays. Antenna-in-package with three-dimensional (3D) or double-side component is widely pursued as the front-up architecture to realize this vision. The interconnect height and losses are critical parameters in these 3D package structures. Copper sintering paste is emerging as an ideal candidate to replace solders for both off-chip and on-package interconnects because of the resulting higher electrical conductivity and relatively simple manufacturability with additive processes. This article focuses on computational modeling, optimization of sintering conditions, and electrical conductivity measurements of highly conductive copper paste to verify the proposed model. The model is based on two-particle sintering theory, which describes the neck growth evolution of copper paste at the initial stage of sintering. The neck-growth model shows good consistency with the measured neck size of copper, and hence can be used to provide guidelines for the sintering conditions of copper paste. The celectrical conductivity measurements suggest that the copper paste sintered at 260°C for 30 min shows a electrical conductivity of 1.4 × 107 S/m, which is 82% higher than that of solder. In addition, this article investigates the potential of copper paste interconnect technology in high-frequency applications such as in 5G millimeter-wave communications. The transmission lines patterned with the copper paste show good correlation with simulated results in the millimeter-wave frequency band. The high-frequency characterization also indicates that the copper paste enables simple circuit patterning, offering equivalent signal losses with plated copper. The detailed analyses discussed in this article suggest the eligibility for multi-applications of copper sintering paste in IC packaging.

Advances in High Performance RDL Technologies for Enabling IO Density of 500 IOs/mm/layer and 8-μm IO Pitch Using Low-k Dielectrics

Abstract: Currently, the IC industry has been steadily advancing towards 7 nm and 5 nm nodes with further reductions projected in the near future to progressively create large number of inputs and outputs (IOs) at finer pitch. Today the high-density interconnect (HDI) organic redistribution layer (RDL) can only achieve an IO density of about 40 IOs per mm per layer with line and space of 6 μm and microvia diameter of 20 μm at 50 μm pitch. However, to achieve further increases in IO density, RDL with 1 μm routing lines and spaces together with 1 to 2 μm diameter microvias are required. Such advances in the RDL technology are of great importance to accomplish IO densities of 500 IOs/mm/layer to enable high bandwidths of 500 Gb/s at low cost. In this paper we present the latest progress at the Packaging Research Center, Georgia Institute of Technology in the following 4 key areas.1. Fine line photolithography: Various methods that can achieve 1 μm critical dimension (CD) are discussed and recent results on 1 μm L/S using both dry film and liquid photoresists together with advanced lithographic tools are presented.2. Small microvia creation: Microvia is the most important barrier limiting the RDL to achieve high IO density and fine IO pitch. In this paper, microvia diameter scaling down to 2 μm along with the feasibility to achieve 1 μm and via pitch of 4 to 8 μm using both photo and picosecond pulsed UV laser will be presented.3. Low Dk and Low Df dielectric materials: Dielectric material layers are an important part of RDL. For achieving multi-functional high speed and/or low loss systems and modules, dielectric layers with low Dk and/or low Df materials are critical. The material requirements, availability and process challenges will be addressed in this paper.4. Process methodology: The semi-additive process (SAP) has been the process of record for RDL fabrication. In this paper, the conventional SAP and its modifications such as modified-SAP (m-SAP) and advanced SAP (a-SAP) together with alternative organic damascene process (ODP) along with back-end- of-line (BEOL) will be reviewed and compared.Finally, considerations for future trends are presented.

Glass Panel Packaging, as the Most Leading-Edge Packaging: Technologies and Applications

Abstract: The semiconductor and systems landscape are changing dramatically. As Moore's law begins to come to an end for many reasons that include minimal increase in transistor performance and in computer performance from node to node but at higher power, the industry has begun to shift to interconnections, referred to as Moore's law for Packaging. This focus addresses both the need for homogeneous and heterogeneous integrations by interconnecting smaller chips and smaller components with higher performance at lower cost and interconnecting them as multichip in 2.5 and 3D architectures. This is also called extending Moore's law, not in a single chip but with multiple chips interconnected horizontally and vertically. This strategy is very consistent with the dramatic and emerging changes in electronic systems such as in HPC, AI and a new era of self-driving and electric cars that potentially think and drive better than humans. This requires device, packaging, and computing architecture paradigms with an entirely different vision and strategy than transistor scaling alone. Packaging, which can be viewed broadly as system scaling, is now viewed as replacing Moore's law for enabling better devices and better systems, unlike in the past. Glass packaging is being developed by Georgia Tech and its industry partners, as the most leading-edge packaging, consistent with the above systems needs in cost, performance, functionality, reliability, and miniaturization. This paper describes the critical glass packaging technologies, their R&D and commercialization status as well as all the current and future applications. It compares and contrasts glass packaging against other leading-edge technologies such as Si and embedded packaging.

Vapor phase infiltration of aluminum oxide into benzocyclobutene-based polymer dielectrics to increase adhesion strength to thin film metal interconnects

Abstract: Interfacial adhesion between metallic thin films and polymers is a critical performance metric for a number of microelectronics and packaging applications. Delamination of metal-polymer interfaces is a frequent failure mode for many multilayer structures, like those used for electronics packaging. Such a failure is even more likely when electronic packages are operated under extreme conditions like high-power, high-temperature, and/or high-humidity operation. Roughening or direct chemical modification of the few layers of atoms that make up the interface is often used to promote adhesion at these interfaces. Here, the authors investigate a new process, vapor phase infiltration, that infiltrates inorganic constituents into the bulk of the polymer, creating an interpenetrating network within the subsurface of the polymer that further enhances interfacial adhesion. For the authors’ model system of copper films on a benzocyclobutene polymer, they are able to increase the interfacial adhesion strength by as much as 3×, resulting in cohesive rather than adhesive failure. The authors attribute this increased interfacial adhesion to physicochemical interlocking of the organic and inorganic phases within the subsurface of the polymer, generating a “root system” that impedes interfacial delamination.

Thermal Aging Reliability of Socketable BGA Packages With Ni–Au-Coated SAC305 Spheres

Abstract: Land grid arrays (LGAs) and ball grid arrays (BGAs) constitute the board-level interconnect technologies for a large number of packaged ICs. These technologies are used in socketing and surface mount (SMT) applications, respectively. The concept of socketable BGA packages, with solder spheres coated with a barrier layer/noble metal coating, was introduced to develop a single package design for processor ICs that are used in both socketing and SMT applications. While this concept has previously been demonstrated, the feasibility of these packages in socketing conditions has not yet been studied. This article assesses the applicability of these packages in socketing by subjecting the packages to thermal aging at a temperature of 120 °C. The change in microstructure with thermal aging along with the consumption of the barrier layer was understood. The joint shear strength evolution with thermal aging and the contamination of the top surface of the spheres was studied by the X-ray photoelectron spectroscopy (XPS) analysis. It was found that the trend for experimental consumption of the barrier layer closely follows the theoretical model predictions. Solid-state solder wicking of the Sn57.6Bi0.4Ag (SBA) solder joint due to creep was confirmed at high homologous temperature for the solder. This, along with grain coarsening over time, led to a decrease in the joint shear strength from 33.5 to 16 MPa. Polymer collars are suggested as a potential solution to prevent the solder wicking and make the package feasible for socketing applications.

Thermal aging reliability of socketable, surface-modified solder BGAs with and without polymer collars

Abstract: Ball Grid Array (BGA) package designs are increasingly used in surface mount applications while Land Grid Array (LGA) designs are predominantly used in socketing. The need to converge to a single package design has been driving the need to enable socketable BGAs. BGA spheres with a noble metal surface provide a stable mechanical contact interface with the socket paddles. These noble contact interfaces, however, have to remain intact through the socketing life of the product, considering accelerated testing temperatures of 100-120 °C. Under such conditions, it has been reported that the solder from the ball-attach joints undergoes solid-state wicking along the surface of the ball, leading to complete Au dissolution and potential undesirable intermetallic formation with the socket paddles, along with a drop in ball shear strength due to depletion of the solder from the joints. This paper discusses the use of polymer collars to address this challenge and improve the thermal aging reliability of packages with surface-modified BGA interconnections. The polymer collars were spin-coated on the package, which was aged alongside a reference package with no collars, at accelerated test temperatures of 100 °C and 120 °C, respectively. XPS studies showed that after 650 h of aging, no Au signal but a strong Sn signal was observed in the package without collars, which confirmed complete solder wicking to the top of the ball, while the Au signal remained for the package with the collars, confirming that polymer collars are effective in inhibiting solid-state solder wicking from the ball-attach joints. The joints with polymer collars also showed mechanical stability throughout thermal aging with a 3X improvement in joint shear strength.

Substrate-Embedded Low-Resistance Solenoid Inductors for Integrated Voltage Regulators

Abstract: Integrated power conversion and delivery are the key to achieve high-efficiency and high-performance data processing. Power inductors with high power density and low dc resistance are the key enabler to realize miniaturized voltage regulators (VRs) with high efficiency. With the integrated voltage regulators (IVRs), interconnection length from the battery to the loads can be dramatically reduced, resulting in lower conduction loss and higher power efficiency. This article demonstrates substrates with embedded high-power-density solenoid inductors with an ultralow dc resistance for the IVRs. By incorporating advanced metal–polymer magnetic composites as the cores, the inductors show a high inductance density of 7 nH/mm2 with an ultralow dc resistance of 10 $\text{m}\Omega $ . With a low thickness of $ , the power inductors can be embedded into substrates and positioned close to the loads to realize the IVRs. A substrate-compatible panel-level process was developed to embed the magnetic-core inductors with high throughput and low cost. Compared with the air-core inductors, the magnetic core achieved four times improvement in inductance for the same dc resistance, indicating substantial footprint reduction and improvement in efficiency.

Cointegration of Single-Mode Waveguides and Embedded Electrical Interconnects for High-Bandwidth Communications

Abstract: This article presents the modeling, development, and demonstration of glass interposer technology with single-mode waveguides (SMWGs) for high-bandwidth communications and embedded trenches for ultrafine copper traces for high-speed electronics. Glass as the substrate for the integration of photonics and electronics exhibits a unique combination of superior properties over silicon, laminates, and polymers. In conjunction with the advantages of glass, shape control of photoimageable dielectric lines during development and cure was developed and optimized. Single-mode polymer waveguides on glass were fabricated and characterized. Sample preparation methods and their impact on the sample edge quality and coupling loss will also be discussed in this article. Overall, this article presents the successful process development and demonstration of 3- $\mu \text{m}$ embedded trenches in the dielectric film for ultrafine copper traces and 2- $\mu \text{m}$ microvias for interlayer interconnects.

Fabrication and reliability demonstration of 5μm redistribution layer using low-stress dielectric dry film

Abstract: Low-stress and low-warpage dielectrics are gaining importance as we move towards large-body Multi-chip Modules (MCMs). This paper demonstrates fabrication of redistribution layer (RDL) with 5 μm linewidth/spacing using a novel low-stress dielectric dry film- PLSF (Panasonic low stress film) as a build-up layer. Microvias formation down to 7 μm diameter has also been demonstrated in this paper. The main feature of PLSF is its low- stress and low-warpage. In this paper, we have studied residual stress characteristics of PLSF and its comparison with the industry-standard dielectric (ISD). The lower tensile modulus of PLSF as compared to ISD results in significantly lower residual stress and warpage on the substrate. Electrical and thermomechanical reliability of RDL with PLSF as build-up layer has also been studied and the results are presented in this paper.

Reliability of Fine-Pitch μ m-Diameter Microvias for High-Density Interconnects

Abstract: Downscaling of package wiring has been the singular focus to achieve higher logic-memory interconnect density to meet next-generation needs for high-bandwidth computing. This article presents, for the first time, a systematic modeling and experimental study of sub-5- $\mu \text{m}$ -diameter microvia reliability. Geometry design considerations and build-up dielectric material properties in evaluating the microvia fatigue life are investigated. Finally, experimental thermal-cycling reliability results of sub-5- $\mu \text{m}$ -diameter microvias are correlated with the modeling results.