Showing papers by "Robert Henderson published in 2009"

Low Dark Count Single-Photon Avalanche Diode Structure Compatible With Standard Nanometer Scale CMOS Technology

Abstract: A single-photon avalanche diode structure implemented in a 130-nm imaging process is reported. The device employs a p-well anode, rather than the commonly adopted p+, and a novel guard ring compatible with recent scaling trends in standard nanometer scale complementary metal-oxide-semiconductor technologies. The 50-mum 2 active area device exhibits a dark count rate of 25 Hz at 20 degC and a photon detection efficiency peak of 28% at 500 nm.

Low Dark Count Single-Photon Avalanche Diode Structure Compatible With Standard Nanometer

Abstract: A single-photon avalanche diode structure imple- mented in a 130-nm imaging process is reported. The device employs a p-well anode, rather than the commonly adopted p , and a novel guard ring compatible with recent scaling trends in standard nanometer scale complementary metal-oxide-semicon- ductor technologies. The 50- m active area device exhibits a dark count rate of 25 Hz at 20 C and a photon detection efficiency peak of 28% at 500 nm.

A 32x32 50ps Resolution 10 bit Time to Digital Converter Array in 130nm CMOS for time Correlated Imaging

Abstract: (SUMMARY e report the design and characterisation of a 32x32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50μm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

A low-noise single-photon detector implemented in a 130 nm CMOS imaging process

Abstract: We report on a new single-photon avalanche diode (SPAD) fabricated in a 130 nm CMOS imaging process. A novel circular structure combining shallow trench isolation (STI) and a passivation implant creates an effective guard ring against premature edge breakdown. Thanks to this guard ring, unprecedented levels of miniaturization may be achieved at no cost of added noise, decreased sensitivity, or timing resolution. The detector, integrated along with quenching and readout electronics, was fully characterized. A second batch of detectors with decreased n-well doping was fabricated, thus reducing the dark count rate (DCR) by several orders of magnitude. To the best of our knowledge, the DCR per unit area achieved in these devices is the lowest ever reported in deep sub-micron CMOS SPADs. Optical measurements show the effectiveness of the guard ring and the high degree of electric field planarity across the sensitive region of the detector. With a photon detection probability (PDP) of up to 36% and a timing jitter of 125 ps at full-width-half-maximum, this SPAD is well-suited for applications such as 3D imaging, fluorescence lifetime imaging, and biophotonics.

A low-noise single-photon detector implemented in a 130 nm CMOS imaging process

Abstract: We report on a new single-photon avalanche diode (SPAD) fabricated in a 130 nm CMOS imaging process. A novel circular structure combining shallow trench isolation (STI) and a passivation implant creates an effective guard ring against premature edge breakdown. Thanks to this guard ring, unprecedented levels of miniaturization may be achieved at no cost of added noise, decreased sensitivity, or timing resolution. The detector, integrated along with quenching and readout electronics, was fully characterized. A second batch of detectors with decreased n-well doping was fabricated, thus reducing the dark count rate (DCR) by several orders of magnitude. To the best of our knowledge, the DCR per unit area achieved in these devices is the lowest ever reported in deep sub-micron CMOS SPADs. Optical measurements show the effectiveness of the guard ring and the high degree of electric field planarity across the sensitive region of the detector. With a photon detection probability (PDP) of up to 36% and a timing jitter of 125 ps at full-width-half-maximum, this SPAD is well-suited for applications such as 3D imaging, fluorescence lifetime imaging, and biophotonics.

A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain

Abstract: A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed, time-interleaved operation is also included within each module. A 32x32-TACs array has been fabricated with a 50-µm pitch in order prove the highly parallel operation and to test uniformity and power consumption issues. The measured time resolution (LSB) is of 160 ps on a 20-ns time range with a uniformity across the array within ±2LSBs, while DNL and INL are 0.7LSB and 1.9LSB respectively. The average power consumption is below 300µW/pixel when running at 500k measurements per second.

A 32×32 50ps resolution 10 bit time to digital converter array in 130nm CMOS for time correlated imaging

Abstract: We report the design and characterisation of a 32×32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50µm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

Individually Addressable AlInGaN Micro-LED Arrays With CMOS Control and Subnanosecond Output Pulses

Abstract: We report the fabrication and characterization of an ultraviolet (370 nm) emitting AlInGaN-based micro-light- emitting diode (micro-LED) array integrated with complementary metal-oxide-semiconductor control electronics. This configuration allows an 8 t 8 array of micro-LED pixels, each of 72-mum diameter, to be individually addressed. The micro-LED pixels can be driven in direct current (dc), square wave, or pulsed operation, with linear feedback shift registers (LFSRs) allowing the output of the micro-LED pixels to mimic that of an optical data transmitter. We present the optical output power versus drive current characteristics of an individual pixel, which show a micro-LED output power of up to 570 muW in dc operation. Representative optical pulse trains demonstrating the micro-LEDs driven in square wave and LFSR modes, and controlled optical pulsewidths from 300 ps to 40 ns are also presented.

A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology

Abstract: We report on the design and characterization of a 32 × 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at ± 0.4 and ±1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50µm in both directions and with a total TDC area of less than 2000µm2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

A 32x32 50ps Resolution 10 bit Time to Digital Converter Array in 130nm CMOS for time Correlated Imaging

Abstract: (SUMMARY e report the design and characterisation of a 32x32 time to digital (TDC) converter plus single photon avalanche diode (SPAD) pixel array implemented in a 130nm imaging process. Based on a gated ring oscillator approach, the 10 bit, 50μm pitch TDC array exhibits a minimum time resolution of 50ps, with accuracy of ±0.5 LSB DNL and 2.4 LSB INL. Process, voltage and temperature compensation (PVT) is achieved by locking the array to a stable external clock. The resulting time correlated pixel array is a viable candidate for single photon counting (TCSPC) applications such as fluorescent lifetime imaging microscopy (FLIM), nuclear or 3D imaging and permits scaling to larger array formats.

Single photon avalanche diodes

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

A CMOS time-resolved fluorescence lifetime analysis micro-system

Abstract: We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented.

Mask-less ultraviolet photolithography based on CMOS-driven micro-pixel light emitting diodes

Abstract: We report on an approach to ultraviolet (UV) photolithography and direct writing where both the exposure pattern and dose are determined by a complementary metal oxide semiconductor (CMOS) controlled micro-pixellated light emitting diode array. The 370 nm UV light from a demonstrator 8 x 8 gallium nitride micro-pixel LED is projected onto photoresist covered substrates using two back-to-back microscope objectives, allowing controlled demagnification. In the present setup, the system is capable of delivering up to 8.8 W/cm2 per imaged pixel in circular spots of diameter approximately 8 microm. We show example structures written in positive as well as in negative photoresist.

Hardware implementation and calibration of background noise for an integration-based fluorescence lifetime sensing algorithm

Abstract: A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime extraction [J. Opt. Soc. Am. A25, 1190 (2008)]. A real-time hardware implementation of the IEM FLIM algorithm suitable for single photon avalanche diode arrays in nanometer-scale CMOS technology is now proposed. The problems of reduced pixel readout bandwidth and background noise are studied and a calibration method suitable for FPGA implementation is introduced. In particular, the relationship between signal-to-noise ratio and background noise is considered based on statistics theory and compared with a rapid lifetime determination method and maximum-likelihood estimator with-without background correction. The results are also compared with Monte Carlo simulations giving good agreement. The performance of the proposed methods has been tested on monoexponential decay experimental data. The high flexibility, wide range, and hardware friendliness make IEM the best candidate for system-on-chip integration to our knowledge.

FPGA implementation of a video-rate fluorescence lifetime imaging system with a 32×32 CMOS single-photon avalanche diode array

Abstract: A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations [1]. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13µm CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological applications. Video-rate fluorescence lifetime imaging has been achieved, by performing parallel 32×32 lifetime calculations, realizing the first, compact, and low-cost FLIM camera.

Resistor-input transconductor including common-mode compensation

Abstract: A resistor-input transconductor includes a circuit configured to generate a common-mode compensation current. The common-mode compensation current is used to compensate for the common-mode voltage of the inputs. A current output of the resistor-input transconductor is proportional to a voltage difference between the two inputs and essentially independent of a common-mode voltage of the two inputs. The resistor input transconductor may be applied in a variety of applications including, for example, communications.

Flip‐chip, micro‐pixellated InGaN light‐emitting diode arrays: attractive sources for micro‐displays, colour conversion, and fluorescence detection

Abstract: Flip-chip micro-pixellated InGaN light-emitting diode (micro-LED) arrays fabricated in both matrix-addressable and individually-addressable formats were presented. Despite different addressing schemes, all these LED arrays exhibited superior device operation performance in terms of power output, emission uniformity, and current handling capability, in contrast to the top-emitting counterparts. With the aid of custom-designed driver circuitry, a wide range of promising applications have been demonstrated by using these micro-light sources including micro-display, colour conversion, and fluorescence detection. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A vertically integrated CMOS micro-system for time-resolved fluorescence analysis

Abstract: We describe a two-chip micro-scale time-resolved fluorescence analyzer integrating excitation, detection and filtering. A new 8×8 array of drivers integrated in standard low-voltage 0.35µm CMOS is bump-bonded to AlInGaN blue micro-pixellated light-emitting diodes (micro-LED). The array is capable of producing sample excitation pulses with a width of 777ps (FWHM) enabling short lifetime fluorophores to be excited. The fluorescence emission is detected by a second, vertically-opposed 16×4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35µm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry. This constitutes the smallest reported solid-state micro-system for fluorescence decay analysis, replacing lasers, photomultiplier tubes, bulk optics and discrete electronics. The system is demonstrated with measurements of fluorescent colloidal quantum dot and Rhodamine samples.

Programmable Gain Amplifier and Transconductance Compensation System

Abstract: A programmable gain amplifier (PGA) system comprises selectable parallel transconductors in a front end, independently selectable serial amplification circuits in a back end. The back end is configured to receive an output of the front end and may include a plurality of current or voltage mode amplifiers in series. The PGA system also includes control circuitry to select a gain configuration for the PGA by selecting selectable components in the front and back ends. The PGA system may additionally include control circuitry configured to change the transconductance of one or more of the front end transconductors such that the gain configurations of the PGA are independent of variations such as those due to temperature and fabrication. The PGA system may be used between a signal receiver and an analog to digital converter.

NMOS-only Class-D output stages based on charge pump architectures

Abstract: An NMOS only Class-D output driver which uses charge pump techniques in a low voltage CMOS technology is presented. Compared to conventional Class-D output stages, the given implementation shows a gate area reduction of 45%, resulting in efficiency improvements. The circuit has been simulated in a 0.13µm process and is implemented using 3.3V I/O devices. The structure does not violate any gate-oxide reliability rules.

A non-uniform resolution step GHz 7-bit flash A/D converter for wideband OFDM signal conversion

Abstract: A 1GHz 7-bits flash A/D converter is fabricated in 90nm CMOS technology to be used as part of an Analog Front End (AFE) for digitising of OFDM communication signals. To extend the receiver bandwidth, input capacitance-reducing techniques are used. The motivation in implementing a non-uniform resolution step and the challenges in its physical implementation are discussed. To further reduce the input capacitance, small geometries are used in the comparator input pair, where the offset is corrected by a number of calibration strategies. The converter achieves extended resolution and SNR, and input bandwidth compared to conventional architectures.

Individually-addressable III-nitride micro-LED arrays for integrated CMOS control

Abstract: We report the characterization of micro-pixellated III-nitride LED arrays giving maximum output per pixel of 5mW in continuous mode and 500pJ per 25ns pulse. These have been integrated with custom CMOS control electronics.