S
Soon-Cheon Seo
Researcher at IBM
Publications - 96
Citations - 2192
Soon-Cheon Seo is an academic researcher from IBM. The author has contributed to research in topics: Layer (electronics) & Gate oxide. The author has an hindex of 19, co-authored 95 publications receiving 1872 citations. Previous affiliations of Soon-Cheon Seo include University at Albany, SUNY.
Papers
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Proceedings ArticleDOI
Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
Nicolas Loubet,Terence B. Hook,Pietro Montanini,Chun Wing Yeung,S. Kanakasabapathy,M. Guillom,Tenko Yamashita,Jingyun Zhang,Xin Miao,Junli Wang,Albert M. Young,Robin Chao,Myounggon Kang,Zuoguang Liu,Su Chen Fan,Bassem Hamieh,Stuart A. Sieg,Yann Mignot,W. Xu,Soon-Cheon Seo,Jae-Yoon Yoo,Shogo Mochizuki,Muthumanickam Sankarapandian,Ohyun Kwon,Adra Carr,Andrew M. Greene,Young-Kwan Park,Frougier Julien,Rohit Galatage,Ruqiang Bao,Jeffrey C. Shearer,Richard A. Conti,Ho Ju Song,Deok-Hyung Lee,Dexin Kong,Y. Xu,Abraham Arceo,Zhenxing Bi,Peng Xu,Raja Muthinti,James Chingwei Li,Robert C. Wong,D. Brown,P. Oldiges,Robert R. Robison,John C. Arnold,Nelson Felix,Spyridon Skordas,John G. Gaudiello,Theodorus E. Standaert,Hemanth Jagannathan,D. Corliss,Myung-Hee Na,Andreas Knorr,T. Wu,Dinesh Gupta,S. Lian,R. Divakaruni,T. Gow,C. Labelle,Seng Luan Lee,Vamsi Paruchuri,Huiming Bu,Mukesh Khare +63 more
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Patent
Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect
Carlos J. Sambucetti,Xiaomeng Chen,Soon-Cheon Seo,Birenda Nath Agarwala,Chao-Kun Hu,Naftali E. Lustig,Stephen E. Greco +6 more
TL;DR: In this article, an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant.
Proceedings ArticleDOI
Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
Kangguo Cheng,Ali Khakifirooz,Pranita Kulkarni,Shom Ponoth,J. Kuss,Davood Shahrjerdi,Lisa F. Edge,A. Kimball,S. Kanakasabapathy,K. Xiu,Stefan Schmitz,Alexander Reznicek,Thomas N. Adam,H. He,Nicolas Loubet,S. Holmes,Sanjay Mehta,D. Yang,A. Upham,Soon-Cheon Seo,J. L. Herman,R. Johnson,Yu Zhu,Paul C. Jamison,Bala S. Haran,Z. Zhu,L. H. Vanamurth,Su Chen Fan,D. Horak,Huiming Bu,Philip J. Oldiges,Devendra K. Sadana,P. Kozlowski,D. McHerron,James A. O’Neill,Bruce B. Doris +35 more
TL;DR: In this paper, the authors present a new ETSOI CMOS integration scheme that incorporates all benefits from their previous unipolar work, and demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at I off = 300 pA/m, V DD = 0.9V, and L G = 25nm.
Journal ArticleDOI
Tantalum Nitride Films Grown by Inorganic Low Temperature Thermal Chemical Vapor Deposition Diffusion Barrier Properties in Copper Metallization
Alain E. Kaloyeros,Xiaomeng Chen,Tanja Stark,Kaushik Kumar,Soon-Cheon Seo,Gregory G. Peterson,Harry L. Frisch,Barry C. Arkles,John Sullivan +8 more
TL;DR: In this article, the performance of chemical vapor deposited (CVD) nitrogen-rich tantalum nitride (TaN x, x ∼ 1.8) films as a diffusion barrier in copper (Cu) based metallization schemes was evaluated.
Proceedings ArticleDOI
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
Ruilong Xie,Pietro Montanini,Kerem Akarvardar,Neeraj Tripathi,Balasubramanian S. Pranatharthi Haran,Scott C. Johnson,Terence B. Hook,Bassem Hamieh,D. Corliss,Junli Wang,Xin Miao,John R. Sporre,Jody A. Fronheiser,Nicolas Loubet,Min Gyu Sung,Stuart A. Sieg,Shogo Mochizuki,Christopher Prindle,Soon-Cheon Seo,Andrew M. Greene,Jeffrey C. Shearer,Andre Labonte,Su Chen Fan,Lars W. Liebmann,Robin Chao,Abraham Arceo,Kisup Chung,K. Cheon,Praneet Adusumilli,H. P. Amanapu,Zhenxing Bi,Jungho Cha,H. Chen,Richard A. Conti,Rohit Galatage,Oleg Gluschenkov,Vimal Kamineni,Ki-chul Kim,Lee Choonghyun,F. Lie,Zuoguang Liu,Sanjay Mehta,Eric R. Miller,Hiroaki Niimi,Chengyu Niu,Chanro Park,D. Park,Mark Raymond,Bhagawan Sahu,Muthumanickam Sankarapandian,Shariq Siddiqui,Richard G. Southwick,Lei Sun,Charan V. V. S. Surisetty,Stan D. Tsai,S. Whang,Peng Xu,Y. Xu,C.-C. Yeh,Peter Zeitzoff,J. Zhang,James Chingwei Li,James J. Demarest,John C. Arnold,Donald F. Canaperi,Derren N. Dunn,Nelson Felix,Dinesh Gupta,Hemanth Jagannathan,S. Kanakasabapathy,Walter Kleemeier,C. Labelle,M. Mottura,P. Oldiges,Spyridon Skordas,Theodorus E. Standaert,Tenko Yamashita,Matthew E. Colburn,Myung-Hee Na,Vamsi Paruchuri,S. Lian,R. Divakaruni,T. Gow,Seng Luan Lee,Andreas Knorr,Huiming Bu,Mukesh Khare +86 more
TL;DR: In this paper, the authors present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology.