C
C. DeWan
Researcher at IBM
Publications - 10
Citations - 396
C. DeWan is an academic researcher from IBM. The author has contributed to research in topics: Copper interconnect & CMOS. The author has an hindex of 6, co-authored 10 publications receiving 371 citations.
Papers
More filters
Proceedings ArticleDOI
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
C-H. Lin,Brian J. Greene,Shreesh Narasimha,J. Cai,A. Bryant,Carl J. Radens,Vijay Narayanan,Barry Linder,Herbert L. Ho,A. Aiyar,E. Alptekin,J-J. An,Michael V. Aquilino,Ruqiang Bao,V. Basker,Nicolas Breil,MaryJane Brodsky,William Y. Chang,Clevenger Leigh Anne H,Dureseti Chidambarrao,Cathryn Christiansen,D. Conklin,C. DeWan,H. Dong,L. Economikos,Bernard A. Engel,Sunfei Fang,D. Ferrer,A. Friedman,Allen H. Gabor,Fernando Guarin,Ximeng Guan,M. Hasanuzzaman,J. Hong,D. Hoyos,Basanth Jagannathan,S. Jain,S.-J. Jeng,J. Johnson,B. Kannan,Y. Ke,Babar A. Khan,Byeong Y. Kim,Siyuranga O. Koswatta,Amit Kumar,T. Kwon,Unoh Kwon,L. Lanzerotti,H-K Lee,W-H. Lee,A. Levesque,Wai-kin Li,Zhengwen Li,Wei Liu,S. Mahajan,Kevin McStay,Hasan M. Nayfeh,W. Nicoll,G. Northrop,A. Ogino,Chengwen Pei,S. Polvino,Ravikumar Ramachandran,Z. Ren,Robert R. Robison,Saraf Iqbal Rashid,Viraj Y. Sardesai,S. Saudari,Dominic J. Schepis,Christopher D. Sheraw,Shariq Siddiqui,Liyang Song,Kenneth J. Stein,C. Tran,Henry K. Utomo,Reinaldo A. Vega,Geng Wang,Han Wang,W. Wang,X. Wang,D. Wehelle-Gamage,E. Woodard,Yongan Xu,Y. Yang,N. Zhan,Kai Zhao,C. Zhu,K. Boyd,E. Engbrecht,K. Henson,E. Kaste,Siddarth A. Krishnan,Edward P. Maciejewski,Huiling Shang,Noah Zamdmer,R. Divakaruni,J. Rice,Scott R. Stiffler,Paul D. Agnello +98 more
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Proceedings ArticleDOI
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
Shreesh Narasimha,Paul Chang,Claude Ortolland,David M. Fried,E. Engbrecht,Karen A. Nummy,Paul C. Parries,Takashi Ando,Michael V. Aquilino,N. Arnold,R. Bolam,Jin Cai,Michael P. Chudzik,Benjamin Cipriany,G. Costrini,Min Dai,Jessica Dechene,C. DeWan,Bernard A. Engel,Michael A. Gribelyuk,Dechao Guo,G. Han,N. Habib,Judson R. Holt,Dimitris P. Ioannou,Basanth Jagannathan,Jaeger Daniel,J. Johnson,W. Kong,J. Koshy,Rishikesh Krishnan,Amit Kumar,Mahender Kumar,Jae Gon Lee,Xiaolin Li,C-H. Lin,Barry P. Linder,S. Lucarini,Naftali E. Lustig,Paul S. McLaughlin,Katsunori Onishi,Viorel Ontalus,Robert R. Robison,Christopher D. Sheraw,Matthew W. Stoker,Alvin G. Thomas,Geng Wang,Richard Wise,L. Zhuang,Gregory G. Freeman,J. Gill,Edward P. Maciejewski,Rajeev Malik,J. Norum,Paul D. Agnello +54 more
TL;DR: A hierarchical BEOL with 15 levels of copper interconnect including self-aligned via processing delivers high performance with exceptional reliability in SOI CMOS 22nm technology.
Proceedings ArticleDOI
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
Michael P. Chudzik,Bruce B. Doris,R. Mo,Jeffrey W. Sleight,E. Cartier,C. DeWan,Dae-Gyu Park,Huiming Bu,Wesley C. Natzle,W. Yan,C. Ouyang,K. Henson,Diane C. Boyd,S. Callegari,R. Carter,D. Casarotto,Michael A. Gribelyuk,M. Hargrove,Wei He,Y. Kim,Barry P. Linder,Naim Moumen,Vamsi Paruchuri,James H. Stathis,Michelle L. Steen,A. Vayshenker,X. Wang,Sufi Zafar,Takashi Ando,Ryosuke Iijima,Mariko Takayanagi,Vijay Narayanan,Richard Wise,Y. Zhang,R. Divakaruni,Mukesh Khare,Tze-Chiang Chen +36 more
TL;DR: In this article, a gate-first integration of band-edge high-κ/metal gate nFET devices with dual stress liners and silicon-on-insulator substrates for the 45nm node and beyond is presented.
Proceedings ArticleDOI
A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric
Ronald D. Goldblatt,Birendra N. Agarwala,M.B. Anand,Edward Barth,G. A. Biery,Z.G. Chen,Stephan A. Cohen,J.B. Connolly,Andy Cowley,Timothy J. Dalton,S Das,Charles R. Davis,Alina Deutsch,C. DeWan,Daniel C. Edelstein,P.A. Emmi,C.G. Faltermeier,John A. Fitzsimmons,J. L. Hedrick,John E. Heidenreich,Chenming Hu,J.P. Hummel,P. Jones,Erdem Kaltalioglu,B.E. Kastenmeier,Mahadevaiyer Krishnan,William F. Landers,Eric G. Liniger,Junjun Liu,Naftali E. Lustig,Sandra G. Malhotra,D.K. Manger,Vincent J. McGahay,R. Mih,Henry A. Nye,Sampath Purushothaman,H. Rathore,Soon-Cheon Seo,Timothy M. Shaw,Andrew H. Simon,Spooner Terry A,M. Stetter,Richard A. Wachnik,J.G. Ryan +43 more
TL;DR: In this paper, the integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described, and the integration is achieved while maintaining reliability standards.
Patent
Photo acid generator compounds, photo resists, and method for improving bias
Gregory Breyta,Phillip J. Brock,Daniel J. Dawson,Ronald A. DellaGuardia,C. DeWan,Andrew R. Eckert,Hiroshi Ito,Premlatha Jagannathan,Leo L. Linehan,Kathleen H. Martinek,Wayne M. Moreau,Randolph Joseph Smith +11 more
TL;DR: Several mid UV photo acid generators (PAGs), a chemically amplified photo resist (CAMP), and a method for improving nested to isolated line bias are provided in this paper, which do not require a mid UV sensitizer.