Showing papers by "Runsheng Wang published in 2023"
TL;DR: In this article , the impact of the top electrodes on the ferroelectricity of hafnium-based thin films is investigated using both theoretical and experimental approaches, and the results show that the strain is the dominant factor for the grain size is large (>10 nm).
Abstract: It is commonly believed that the impact of the top electrodes on the ferroelectricity of hafnium-based thin films is due to strain engineering. However, several anomalies have occurred that put existing theories in doubt. This work carries out a detailed study of this issue using both theoretical and experimental approaches. The 10 nm Hf0.5Zr0.5O2 (HZO) films are prepared by atomic layer deposition, and three different top capping electrodes (W/MO/ITO) are deposited by physical vapor deposition. The electrical testing finds that the strain does not completely control the ferroelectricity of the devices. The results of further piezoelectric force microscopy characterization exclude the potential interference of the top capping electrodes and interface for electrical testing. In addition, through atomic force microscopy characterization and statistical analysis, a strong correlation between the grain size of the top electrode and the grain size of the HZO film has been found, suggesting that the grain size of the top electrode can induce the formation of the grain size in HZO thin films. Finally, the first-principles calculation is carried out to understand the impact of the strain and grain size on the ferroelectric properties of HZO films. The results show that the strain is the dominant factor for ferroelectricity when the grain size is large (>10 nm). However, when the grain size becomes thinner (<10 nm), the regulation effect of grain sizes increases significantly, which could bring a series of benefits for device scaling, such as device-to-device variations, film uniformity, and domain switch consistency. This work not only completes the understanding of ferroelectricity through top electrode modulation but also provides strong support for the precise regulation of ferroelectricity of nanoscale devices and ultrathin HZO ferroelectric films.
3 citations
TL;DR: In this article , an interactive layout editing system is presented that includes well-defined commands for both placement and routing customization for analog layout design, which is capable of handling real-time user interaction and improving the performance of fully automated layout generators verified by post-layout simulation.
Abstract: Analog layout design is still primarily reliant on manual efforts. Current fully automated workflows are unable to meet the expectations for flexible customization and are incompatible with existing manual workflows. For both performance and productivity, interactive layout editing has the ability to bridge the gap between manual and automated flows. We present an interactive layout editing system in this study that includes well-defined commands for both placement and routing customization. This is a pioneering work that provides a holistic study on the interactive design methodology for analog layouts and its capability of speeding up design closure. Our framework comes up with the instant placement legalization and routing adjustment mechanism for rapid layout update and modification. The framework is capable of handling real-time user interaction and improving the performance of fully automated layout generators verified by post-layout simulation on real-world analog designs. Experimental results demonstrate the performance enhancement on real-world analog designs with only a few editing commands. As examples, on the low-dropout regulator, our framework can reduce the overshot down and up voltage to nearly $1/3$ of layout generated by automation tool with two editing commands, and on the operational transconductance amplifier, it achieves 33.5% better common mode rejection ratio with only one command.
1 citations
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TL;DR: In this article , the physics mechanisms in off-state degradation are proposed by combining TCAD simulations and comprehensive experimental characterizations, which leads to a compact reliability model reported in part II.
Abstract: Previous works on transistor reliability are mostly devoted to ON-state degradations, such as bias temperature instability and hot carrier degradation, for which physical models have been developed to describe corresponding mechanisms. However, very limited data on OFF-state degradation is available, especially in FinFET technology. In the first part of this article, OFF-sate degradations of 7-nm FinFET technology are reported for the first time. The physics mechanisms in OFF-state degradation are proposed by combining TCAD simulations and comprehensive experimental characterizations. It is found that an enhanced secondary carriers effect is responsible for the OFF-state degradation with contributions from both trapped electrons and holes. Furthermore, typical locations of electron traps and hole traps under the OFF-state degradation are identified. The abnormal leakage degradation is explained in a consistent manner. The analysis here leads to a compact reliability model reported in part II.
1 citations
TL;DR: In this article , the concept of critical transistors, which can be extracted by sensitivity analysis, is introduced to reduce the number of SPICE simulations during the characterization of the aging-aware library.
Abstract: With transistor scaling to nanometer region, aging effects become a non-neglectable issue in circuit design. Aging-aware standard cell library is necessary for robust circuit design. To consider aging effects in standard cell libraries, existing methods mostly require simulating all combinations of aging variables and timing arcs, which are unscalable to large cells. In this brief, we propose an efficient aging-aware standard cell library characterization framework based on sensitivity analysis. We introduce the concept of critical transistors, which can be extracted by sensitivity analysis. By specifying these critical transistors, the number of SPICE simulations can be significantly reduced during the characterization of the aging-aware library. Experimental results on characterizing the standard cells in 16/14nm technology node demonstrate that the proposed method can achieve 1% average relative error and 1.48% maximum relative error with 4.9 $\times $ to 305 $\times $ speedup, compared with the state-of-the-art work. The method is very flexible and can be deployed into commercial electronic design automation (EDA) tools and libraries.
1 citations
TL;DR: In this article , the essential physics of the ferroelectric tunnel junction (FTJ) are assessed with technology computer-aided design (TCAD) simulations and analytical models, and the full regions of the FTJ operations, including the read/write, are explored.
Abstract: The essential physics of the ferroelectric tunnel junction (FTJ) is assessed with technology computer-aided design (TCAD) simulations and analytical models. With experimental data calibrations, a TCAD simulation framework including electrostatic potentials, ferroelectric (FE) polarizations, and nonlocal tunneling is built. Full regions of the FTJ operations, including the read/write, are then explored. Key parameters such as the memory state threshold voltages ( ${V}_{\text {mth}}$ ) and the region boundary voltages are defined, and their model formulations are developed. With the essential physics captured, FTJ figure-of-merits (FoMs) are accessed with not only tunneling electroresistance (TER), but also power consumption. Design parameters from FE layer thickness, polarizations, and coercive field to silicon doping and metal work functions are studied, with their impacts on key FTJ FoMs evaluated.
07 Mar 2023
TL;DR: In this paper , the authors present a trap-based approach to model bias temperature instability (BTI), hot carrier degradation (HCD), and mixed-mode transistor reliability. But the authors focus on the degradation and recovery of the hot carrier.
Abstract: In this paper, the recent advances of our studies on the compact aging modeling of bias temperature instability (BTI), hot carrier degradation (HCD) and mixed-mode transistor reliability are presented from trap-based approaches. Origins of BTI with contributions from different types of traps are identified from advanced characterization techniques. An open-source BTI model, with the industry-standard model interface OMI and the capability of capturing both degradation and recovery, has been developed for SPICE simulation and Design-Technology Co-optimization (DTCO). Three types of traps also have been identified from experiments in HCD, and a unified model has been proposed which can accurately predict HCD in full Vgs/Vds bias. Finally, the mixed-mode reliability of HCD-BTI coupling, through self-heating or under off-state stress, is discussed.
TL;DR: In this paper , a compact, robust, and transposable SRAM in-memory computing (IMC) macro is presented to support feed forward (FF) and back propagation (BP) computation within a single macro.
Abstract: This article presents a compact, robust, and transposable SRAM in-memory computing (IMC) macro to support feed forward (FF) and back propagation (BP) computation within a single macro. The transpose macro is created with a clustering structure, and eight 6T bitcells are shared with one charge-domain computing unit (CCU) to efficiently deploy the DNNs weights. The normalized area overhead of clustering structure compared to 6T SRAM cell is only 0.37. During computation, the CCU performs robust charge-domain operations on the parasitic capacitances of the local bitlines in the IMC cluster. In the FF mode, the proposed design supports 128-input 1b XNOR and 1b AND multiplications and accumulations (MACs). The 1b AND can be extended to multi-bit MAC via bit-serial (BS) mapping, which can support DNNs with various precision. A power-gated auto-zero Flash analog-to-digital converter (ADC) reducing the input offset voltage maintains the overall energy efficiency and throughput. The proposed macro is prototyped in a 28-nm CMOS process. It demonstrates a 1b energy efficiency of $166\vert 257$ TOPS/W in FF-XNOR $\vert $ AND mode, and 31.8 TOPS/W in BP mode, respectively. The macro achieves $80.26\% \vert 85.07\%$ classification accuracy for the CIFAR-10 dataset with 1b $\vert 4\text{b}$ CNN models. Besides, 95.50% MNIST dataset classification accuracy (95.66% software accuracy) is achieved by the BP mode of the proposed transpose IMC macro.
TL;DR: In this article , an equiprobability-based local response surface (ELRS) method was proposed to perform high-sigma yield estimation with both high accuracy and efficiency, and the proposed method exhibits more than ten times improvement in accuracy when compared with the state-of-the-art.
Abstract: With the ever-increasing transistor density and memory capability in integrated circuits, the high-sigma yield estimation has become a growing concern. This work presents an equiprobability-based local response surface (ELRS) method that can perform a high-sigma yield estimation with both high accuracy and efficiency. Demonstrating with 6T-SRAM, the proposed method exhibits more than ten times improvement in accuracy when compared with the state-of-the-art while maintaining the efficiency to the best record in the literature.
TL;DR: HybridNet as mentioned in this paper constructs two individual graphs (geometry-graph, topology-graph) with distinct edge construction schemes according to their unique properties, and then proposes a dual-branch network with different encoder layers in each pathway and aggregate representations with a sophisticated fusion strategy.
Abstract: Accurate early congestion prediction can prevent unpleasant surprises at the routing stage, playing a crucial character in assisting designers to iterate faster in VLSI design cycles. In this paper, we introduce a novel strategy to fully incorporate topological and geometrical features of circuits by making several key designs in our network architecture. To be more specific, we construct two individual graphs (geometry-graph, topology-graph) with distinct edge construction schemes according to their unique properties. We then propose a dual-branch network with different encoder layers in each pathway and aggregate representations with a sophisticated fusion strategy. Our network, named HybridNet, not only provides a simple yet effective way to capture the geometric interactions of cells, but also preserves the original topological relationships in the netlist. Experimental results on the ISPD2015 benchmarks show that we achieve an improvement of 10.9% compared to previous methods.
TL;DR: In this article , a short-term Negative Bias Temperature Instability (NBTI) was investigated in sub-20-nm DRAM technology by using Variable Amplitude Charge Pumping measurement.
Abstract: Short-term Negative Bias Temperature Instability (NBTI) was investigated in sub-20-nm DRAM technology. By using Variable $\text{T}_{\text {charge}}$ - $\text{T}_{\text {discharge}}$ Amplitude Charge Pumping measurement, ultra-fast traps can be characterized with high accuracy. Both electron traps and hole traps are identified in the transistor. The energy and spatial distribution for these two traps can be clearly extracted. By further comparing with ab-initio calculation, the electron traps are found to relate to dangling bonds and hole traps originate from oxygen vacancies. Electron traps can contribute up to 90% in short-term NBTI and thus could be critical for future improvement. The results are useful in understanding the reliability of sub-20nm DRAM technology.
TL;DR: In this article , the authors used tungsten as the capping electrode and replaced the conventional HZO layer with a stacked HfO2-ZrO2 superlattice with optimized oxygen vacancy distribution and improved crystallinity.
Abstract: The hafnium-zirconium oxide (HZO) has been reported to be a promising candidate for low-power VLSI logic and memory applications. However, the demand for high processing temperatures above 500 °C keeps it away from the Back-End-of-Line (BEOL) process. Many reports have explored various methods to facilitate the formation of orthorhombic phases at lower temperatures, but these methods have typically resulted in low remnant polarization ( ${P}\text{r}$ ) and poor reliability due to poor crystallinity and oxygen vacancy (Ov) accumulation. To address these challenges, we have chosen tungsten (W) as the capping electrode due to its superior capability for inducing orthorhombic phases. We have also replaced the conventional HZO layer with a stacked HfO2-ZrO2 superlattice with optimized Ov distribution and improved crystallinity. As a result, our sample processed at 400 °C exhibits a maximum $2{P}\text{r}$ of $32 ~\mu \text{C}$ /cm2 at 2.5 MV/cm. It demonstrates the stable endurance cycles up to ${2} \times {10} ^{{9}}$ exceeding the performance of the W-HZO control sample and remaining competitive with the most recent results in the literature.
01 Apr 2023
TL;DR: In this paper , the authors proposed the first current-programming eDRAM CIM that unifies the weight programming and computing in the current domain and achieved the highest macro-level 4b-MAC energy efficiency.
Abstract: The smart edge nodes require efficient matrix-vector multiplications for local deep neural network (DNN) inference. Benefiting from its high density and CMOS compatibility, the eDRAM-based computing-in-memory (CIM) [1] –[4], especially with multi-level cells (MLCs) [4], attracts rising attention. However, the performance of prior MLCeDRAM CIM is severely limited by the inconsistency of weight representations during the programming and computing: weights are programmed as fixed voltages while transistor currents are used for computation. Thus, the programming of MLCs requires calibration due to the nonlinear transistor I-V, which can be extremely complicated in the presence of $V_{T H}$ variations. Furthermore, the computing precision is severely degraded by $\mathrm{V}_{\mathrm{TH}}$ variations when small computing currents are used for high parallelism. To fundamentally surmolunt this dilemma, we propose the first currentprogramming eDRAM CIM that unifies the weight programming and computing in the current domain. The enabling technique is a novel 3T1C eDRAM cell (Fig. 1, top right). It confers several key merits: 1) the cell is programmed by the weight current directly with the selfcalibrated voltage generated on the storage capacitor; it essentially stores the weight current instead of a fixed voltage, thus mitigating $V_{\text {TH}}$ variation and nonlinear transistor I-V impacts; 2) a dynamiccascoded read structure is proposed to significantly reduce the VB sensitivity while not requiring any bias voltage; 3) thanks to the accurately programmed cell, it supports MLC operation (8 current levels) without any calibration, largely increasing density; 4) a voltage-current two-step programming scheme significantly boosts the sub- $\mu \mathrm{A}$ current-weight writing speed. Combining these merits, the proposed eDRAM cell is naturally immune to transistor-level nonidealities, thus allowing a small LSB weight current of only 100nA. A $4 \mathrm{~b}$ CIM cell composed of 2MLCs is developed to support 4bsigned weights. It contains 15 current levels ranging from -700nA to 700nA. Fabricated in a $65 \mathrm{~nm}$ CMOS, the prototype achieves the highest macro-level 4b-MAC energy efficiency of 233-305TOPS/W among eDRAM CIMs.
TL;DR: CircNet as discussed by the authors is a large-scale dataset for machine learning tasks in VLSI CAD, which consists of more than 10k samples extracted from versatile runs of commercial design tools based on 6 open-source RISC-V designs.
Abstract: The design automation community has been actively exploring machine learning for VLSI CAD. Many studies have explored learning-based techniques for cross-stage prediction tasks in the design flow. Although building machine learning models usually requires a large amount of data, most studies can only generate small internal datasets for validation due to the lack of large public datasets. Such a situation challenges the research in this field and raises potential issues like difficulty in benchmarking and reproducing results, limited research scope on small internal datasets, and high bar for new researchers. Therefore, in this paper, we present an open-source dataset called “CircuitNet” for machine learning tasks in VLSI CAD. The dataset consists of more than 10K samples extracted from versatile runs of commercial design tools based on 6 open-source RISC-V designs which support typical cross-stage prediction tasks, such as routability and IR drop prediction, with extensive benchmarking on recent models. With the dataset prepared, we identify two practical challenges, data imbalance and model transferability, for machine learning application in CAD. To overcome data imbalance, we propose a loss function, biased loss, to give more weight to the minority, leading to 2% congestion reduction in routability driven placement. We test the model transferability from RISC-V designs to ISPD 2015 contest designs in congestion prediction with several transfer learning methods, and further proposed a knowledge distillation based transfer learning framework with up to 20% accuracy improvement. We believe this dataset can open up new opportunities for machine learning in CAD research and beyond.
01 Mar 2023
TL;DR: In this paper , the double-sided row hammer effect at the silicon level for sub-20 nm dynamic random access memory (DRAM) was systematically investigated for the first time based on 3D TCAD simulation, the impacts of capacitive crosstalk and electron migration were investigated.
Abstract: The double-sided row hammer (rh) effect at the silicon level for sub-20 nm dynamic random access memory (DRAM) is systematically investigated for the first time. Based on 3D TCAD simulation, the impacts of capacitive crosstalk and electron migration are investigated. The latter with trap assistance is found the dominant mechanism behind the enhancement of 1 failure and the alleviation of 0 failure for double-sided rh. Moreover, rh dependences on data pattern, timing parameters and technology nodes are compared under different rh conditions. A trade-off of retention time (tret) between 1 failure and 0 failure should be considered when suppressing the double-sided rh effect. With the co-optimization of key process parameters, tret for double-sided rh-induced 1 failure can be improved by 220 times.
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TL;DR: In this paper , a compact aging model of off-state degradation in advanced FinFETs is developed and validated by silicon data of 7-nm node, including the degradation and recovery phases.
Abstract: Part I of this article revealed that the OFF-state degradation consists of both bias temperature instability (BTI) and hot carrier degradation (HCD) traps in different channel regions. In part II of this article, a compact aging model of OFF-state degradation in advanced FinFETs is developed and validated by silicon data of 7-nm node, including the degradation and recovery phases. The model is capable to cover various types of devices, such as n/p types, core/IO devices, with short/long-channels. Meanwhile, trap contributions over time in different types of FinFETs are discussed based on the model component analysis. The model is implemented into circuit simulators and used to predict circuit aging with OFF-state degradation, for example, a ring oscillator (RO) circuit. The extrapolation result shows that up to 25% degradation is underestimated if the OFF-state reliability is not considered. This work provides a solution for more accurate reliability evaluation of nanoscale circuit design.
01 Mar 2023
TL;DR: In this article , the body bias effect after hot carrier degeneration was observed in 7 and 5nm FinFETs, even though they had negligible body bias dependence before HCD.
Abstract: In this paper, we observed non-negligible body bias effect after hot carrier degeneration (HCD) in 7 and 5nm FinFET technologies, even though they have negligible body bias dependence before HCD. We revealed that the trap-induced partial shift of the channel current towards the bottom of fin is the culprit for the enhanced body-biased effect, by combining TCAD and experimental results. We also studied mobility modulation by body bias effect before and after degradation. The results are beneficial for the reliability-aware circuit design against HCD particularly for FinFET-based circuits.
01 Apr 2023
TL;DR: In this article , the authors investigated the robustness of deep neural networks against various perturbations like adversarial noise and hardware faults, such as hardware faults and the model's robustness.
Abstract: Deep neural networks (DNNs) have revolutionized different applications ranging from computer vision to natural language processing, and are widely deployed in data centers and edge devices. It can be foreseen that DNNs will be applied in more and more safety-critical applications like autonomous driving and robotics, which typically require highly reliable computing to avoid catastrophic consequences. Therefore, not only the model's robustness against various perturbations like adversarial noise, but also the robustness of the silicon-based accelerators to hardware faults needs to be comprehensively investigated [1], [2].
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TL;DR: In this article , a dynamic compact model for metal-ferroelectric-semiconductor (MFS) ferroelectric tunnel junctions (FTJ) based on their device physics is proposed.
Abstract: In this letter, we proposed a dynamic compact model for metal-ferroelectric-semiconductor (MFS) ferroelectric tunnel junctions (FTJ) based on their device physics. The voltage control over dynamic polarizations and the semiconductor surface potentials is achieved for full-region operations, supporting complex FTJ state transitions. A unified and smooth current model across different regions was proposed by formulating tunneling transports in FTJ with complicated barrier shapes from the first-principle tunneling theory. The model was extensively verified with both experimental data and technology computer-aided design (TCAD) simulations, featuring accurate descriptions of multi-states, frequency dependent programming, and circuit simulations.
01 Apr 2023
TL;DR: SAGERoute as mentioned in this paper is a synergistic routing framework taking both geometric and electrical constraints into consideration, through Steiner tree based wire sizing and guided detailed routing, the framework can generate high-quality routing solutions efficiently under versatile constraints on real world analog designs.
Abstract: Routing is critical to the post-layout performance of analog circuits. As modern analog layouts need to consider both geometric constraints (e.g., design rules and low bending constraints) and electrical constraints (e.g., electromigration (EM), IR drop, symmetry, etc.), it becomes increasingly challenging to investigate the complicated design space. Most previous work has focused only on geometric constraints or basic electrical constraints, lacking holistic and systematic investigation. Such an approach is far from typical manual design practice and can not guarantee post-layout performance on real-world designs. In this work, we propose SAGERoute, a synergistic routing framework taking both geometric and electrical constraints into consideration. Through Steiner tree based wire sizing and guided detailed routing, the framework can generate high-quality routing solutions efficiently under versatile constraints on real-world analog designs.
TL;DR: AVATAR as discussed by the authors is an aging-and variation-aware dynamic timing analyzer that can perform DTA with the impact of transistor aging and random process variation, including the gate-level aging analysis and random variation model that can accurately calculate cell delay under the impact on transistor aging, and an event-based DTA algorithm that avoids the pessimistic property of graphbased analysis.
Abstract: As the timing guardband consumes more and more design margin with the technology scaling, better-than-worst-case (BTWC) techniques have gained more attention as a promising solution. BTWC techniques can relax the design margin by transcending the pessimistic static timing constraints and utilizing the dynamic timing information. However, to guarantee the design reliability throughout the lifetime, the conventional dynamic timing analysis (DTA) engines need an extra reliability guardband, which is commonly evaluated under the worst-case corners of aging and variation. This type of guardbanding consumes the precious design margin, thus hindering the efficiency improvement from BTWC techniques. Therefore, in this paper, we propose AVATAR, an aging-and variation-aware dynamic timing analyzer that can perform DTA with the impact of transistor aging and random process variation, including the gate-level aging analysis and random variation model that can accurately calculate cell delay under the impact of transistor aging and random variation, and an event-based DTA algorithm that avoids the pessimistic property of graph-based analysis. We also propose an ML-assisted DTA acceleration flow for the multicycle DTA of homogeneous multicore designs. We present two case studies using AVATAR to show its effectiveness. First, we present an application-based dynamic-voltage-frequency-scaling (DVFS) design methodology based on AVATAR, which can exploit application-level dynamic timing slack (DTS) to improve energy efficiency and performance. The results demonstrate that, compared to the design based on the conventional corner-based DTA, the additional performance improvement of the design based on AVATAR can be up to 14% or the additional power-saving can be up to 20%. Second, we demonstrate using the proposed ML-assisted acceleration flow for reliability-aware deep neural network (DNN) accelerator simulation. We use the proposed flow to estimate the impact of timing errors due to aging and random variation on the inference accuracy of two benchmark DNNs. The results demonstrate that the proposed acceleration flow achieves up to 10W speedup with an average error of less than 2%.
TL;DR: In this paper , the spatial re-scaling and channel-wise shifting are proposed to improve the performance of binary convolutional neural networks for image super-resolution (SR).
Abstract: While the performance of deep convolutional neural networks for image super-resolution (SR) has improved significantly, the rapid increase of memory and computation requirements hinders their deployment on resource-constrained devices. Quantized networks, especially binary neural networks (BNN) for SR have been proposed to significantly improve the model inference efficiency but suffer from large performance degradation. We observe the activation distribution of SR networks demonstrates very large pixel-to-pixel, channel-to-channel, and image-to-image variation, which is important for high performance SR but gets lost during binarization. To address the problem, we propose two effective methods, including the spatial re-scaling as well as channel-wise shifting and re-scaling, which augments binary convolutions by retaining more spatial and channel-wise information. Our proposed models, dubbed EBSR, demonstrate superior performance over prior art methods both quantitatively and qualitatively across different datasets and different model sizes. Specifically, for x4 SR on Set5 and Urban100, EBSRlight improves the PSNR by 0.31 dB and 0.28 dB compared to SRResNet-E2FIF, respectively, while EBSR outperforms EDSR-E2FIF by 0.29 dB and 0.32 dB PSNR, respectively.
TL;DR: In this article , a coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed, which can explain the trap time constants, leading to the trap characterizations in their energy profiles.
Abstract: A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs.