Proceedings ArticleDOI
256 Mb DRAM technologies for file applications
Goro Kitsukawa,Masashi Horiguchi,Y. Kawaijiri,Takayuki Kawahara,T. Aikiba,Yasushi Kawase,Toshikazu Tachibana,T. Sakai,Mayu Aoki,Shoji Shukuri,Kazuhiko Sagara,Ryo Nagai,Norio Hasegawa,Natsuki Yokoyama,T. Kisu,Hiroki Yamashita,Tokuo Kure,Takashi Nishida +17 more
- pp 48-49
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TLDR
The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications and a subthreshold-current limiting scheme for word drivers, which features subarray-by-subarray replacement instead of the conventional line- by-line replacement.Abstract:Â
The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders, and the total data-retention current is less than that of a 64-Mb DRAM. A redundancy technique is shown which features subarray-by-subarray replacement instead of the conventional line-by-line replacement. To evaluate the circuit technologies described here, an experimental 256-Mb DRAM was fabricated using 0.25- mu m CMOS technology with phase-shift lithography. It uses a 0.72- mu m/sup 2/ RSTC cell with a storage capacitance of 25 fF and operates on a voltage of 1.5-3.6 V. >read more
Citations
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Journal ArticleDOI
Trends in low-power RAM circuit technologies
K. Itoh,K. Sasaki,Y. Nakagome +2 more
TL;DR: In this article, a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs, is discussed, and the authors also show that the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks is indispensable in the future.
Journal ArticleDOI
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's
TL;DR: In this paper, a switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of sub-threshold current with threshold-voltage scaling.
Journal ArticleDOI
A semi-static complementary gain cell technology for sub-1 V supply DRAM's
TL;DR: In this article, a semi-static complementary gain cell for low power DRAM's is proposed and experimentally demonstrated, which consists of a write-transistor and its opposite conduction type read-transistors with a heating gate as a storage node which causes a shift in the threshold voltage.
Journal ArticleDOI
Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)
TL;DR: In this paper, the authors presented an analytical expression for sub-threshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment.
Proceedings ArticleDOI
Trends in low-power RAM circuit technologies
K. Itoh,K. Sasaki,Y. Nakagome +2 more
TL;DR: In this paper, a review of low-power RAM circuit technologies is presented, and the following contributions have made possible a DRAM active power reduction of as much as 2 to 3 orders of magnitude over the last decade: lowering operating voltage by lowering the external supply voltage, half-V/sub DD/ data-line precharging and on-chip voltage down converting; reducing charging capacitance through partial activation of multi-divided array, and CMOS NAND decoder.
References
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Journal ArticleDOI
A flexible redundancy technique for high-density DRAMs
TL;DR: In this paper, a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures, which features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair.
Journal ArticleDOI
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM
Y. Nakagome,K. Itoh,Kan Takeuchi,E. Kume,Tanaka Haruhiko,Masanori Isoda,T. Musha,Toru Kaga,T. Kisu,Takashi Nishida,Yoshifumi Kawamoto,Mayu Aoki +11 more
TL;DR: In this article, a circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip.
Proceedings ArticleDOI
A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography
Kazuhiko Sagara,Tokuo Kure,Shoji Shukuri,J. Yugami,Norio Hasegawa,H. Shinriki,H. Goto,H. Yamashita,Eiji Takeda +8 more
TL;DR: In this article, a recessed stacked capacitor (RSTC) structure was used to achieve fine-pattern delineation and high cell capacitance in an experimental memory array with 0.25 mu m phase-shift lithography and CVD-W plate technology.
Proceedings Article
Circuit Techniques for 1.5-3.6V Battery-Operated 64Mb DRAMs
Y. Nakagome,K. Itoh,Kan Takeuchi,E. Kume,Tanaka Haruhiko,T. Mushya,Toru Kaga,T. Kisu,Takashi Nishida,Yoshifumi Kawamoto,Mayu Aoki +10 more
TL;DR: In this article, the authors proposed circuit techniques for battery-operated DRAM's which cover supply voltages from 1.5 to 3.6 V (universal V), as well as their applications to an experimental 64-Mb DRAM.
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