Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely suitable for depositing uniform and conformal films on complex three-dimensional topographies. The deposition of a film of a given material by ALD relies on the successive, separated, and self-terminating gas–solid reactions of typically two gaseous reactants. Hundreds of ALD chemistries have been found for depositing a variety of materials during the past decades, mostly for inorganic materials but lately also for organic and inorganic–organic hybrid compounds. One factor that often dictates the properties of ALD films in actual applications is the crystallinity of the grown film: Is the material amorphous or, if it is crystalline, which phase(s) is (are) present. In this thematic review, we first describe the basics of ALD, summarize the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD [R. L. Puurunen, J. Appl. Phys. 97, 121301 (2005)], and give an overview of the status of processing ternary compounds by ALD. We then proceed to analyze the published experimental data for information on the crystallinity and phase of inorganic materials deposited by ALD from different reactants at different temperatures. The data are collected for films in their as-deposited state and tabulated for easy reference. Case studies are presented to illustrate the effect of different process parameters on crystallinity for representative materials: aluminium oxide, zirconium oxide, zinc oxide, titanium nitride, zinc zulfide, and ruthenium. Finally, we discuss the general trends in the development of film crystallinity as function of ALD process parameters. The authors hope that this review will help newcomers to ALD to familiarize themselves with the complex world of crystalline ALD films and, at the same time, serve for the expert as a handbook-type reference source on ALD processes and film crystallinity.

Crystallinity of inorganic films grown by atomic layer deposition: Overview and general trends

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

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High-K materials and metal gates for CMOS applications

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

Thin films of metallic iridium were grown by atomic layer deposition (ALD) in a wide temperature range of 225-375°C from tris(2,4-pentanedionato)iridium and oxygen. The films had low resistivity and low impurity contents and good adhesion to the substrate. The film growth rate saturated to a constant value as the precursor pulse times were increased, thus verifying the self-limiting growth mechanism. In addition, the film thickness depended linearly on the number of deposition cycles. The development of the surface morphology with increasing film thickness was studied by atomic force microscopy (AFM). AFM and X-ray reflectivity analysis showed that the films had smooth surfaces. The films showed a preferred (111) orientation as studied by X-ray diffraction. The results show that high-quality iridium films can be grown by ALD. © 2004 The Electrochemical Society. All rights reserved.

Atomic Layer Deposition of Iridium Thin Films

We report on the effects on water oxidation performance of varying (1) the nanoscale TiO2 thickness and (2) the catalyst material in catalyst/TiO2/SiO2/Si anodes. Uniform films of atomic layer deposited TiO2 are prepared in the thickness range ∼1–12 nm on degenerately-doped p+-Si, yielding water oxidation overpotentials at 1 mA cm−2 of 300 mV to 600 mV in aqueous solution (pH 0 to 14). Electron/hole transport through Schottky tunnel junction structures of varying TiO2 thickness was studied using the reversible redox couple ferri/ferrocyanide. The dependence of the water oxidation overpotential on ALD-TiO2 thickness, with all other anode design features unchanged, exhibits a linear trend corresponding to ∼21 mV of added overpotential at 1 mA cm−2 per nanometer of TiO2 for TiO2 thicknesses greater than ∼2 nm. For thinner TiO2 layers, an approximately thickness-independent overpotential is observed. The linear behavior for anodes with thicker TiO2 layers is consistent with the predicted effect of bulk TiO2-limited electronic conduction on the voltage required to sustain the current density across the TiO2/SiO2 insulator stack. Eight different oxygen evolution catalysts of thickness 1–3 nm are studied. For the anodes investigated, 3 nm of Ir or Ru gave the best water oxidation performance, but both thinner layers and other catalysts can be quite effective, suggesting the potential for reduced materials cost. Lastly, a flat band voltage analysis of solid state thin film capacitors was done for five different gate metals on n-Si to probe junction energetics directly relevant to a photoanode. The results are consistent with a Schottky junction in which the Fermi level at the semiconductor surface is unpinned.

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Effects of catalyst material and atomic layer deposited TiO2 oxide thickness on the water oxidation performance of metal–insulator–silicon anodes

As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 nm and below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high-k) gate oxide. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled to 10 A equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other gate stack scaling concerns like boron penetration and elevated gate resistance. Extensive simulations have shown that the optimal gate work functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-type MOSFETs (p-type MOSFETs). This study summarizes the evaluations of TiN, Ta–Si–N, WN, TaN, TaSi, Ir, and IrO2 as candidate metals for dual-metal gate complementary metal–oxide semiconductor using HfO2 as the gate dielectric. The gate work function was determined ...

Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics

Thin strained Si layers grown on SiGe layers graded to 20% Ge were studied for resistance to relaxation. It was observed that in the presence of ∼105/cm2 threading dislocations from the underlying graded layers, the barrier to misfit dislocation formation is sufficiently reduced to induce relaxation in Si layers even when the layer thickness is less than the predicted critical thickness. Raman spectroscopy revealed that elastic strain accumulation in the uniform SiGe layers is a significant contributor to strain relaxation in the Si cap layers. Upon annealing, thermal mismatch causes the Si layers to relax further, but most of the strain relaxation is accommodated by elastic strain increase in the SiGe layers. This prevents the rampant increase in defect density that would otherwise accompany the strain relaxation. Annealing in an oxidizing ambient appears to pin pre-existing threading dislocations causing nucleation of new threading dislocations and short misfit segments to relieve the thermal mismatch s...

Relaxation of strained Si layers grown on SiGe buffers

In this study, the authors investigated the addition of zirconium (Zr) into HfO2 to improve its dielectric properties. HfxZr1−xO2 films were deposited by atomic-layer deposition at 200–350°C and annealed in a nitrogen ambient environment at 1000°C. Extensive physical characterization of the impact of alloying Zr into HfO2 is studied using vacuum ultraviolet spectroscopy ellipsometry, attenuated total reflectance Fourier transform infrared spectroscopy, secondary-ion mass spectrometry, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectrometry, and x-ray reflectometry. HfxZr1−xO2 transistors are fabricated to characterize the impact of Zr addition on electrical thickness, mobility, and reliability. Zr addition into HfO2 leads to changes in film microstructure and grain-size distribution. HfxZr1−xO2 films have smaller and more uniform grain size compared to HfO2 for all deposition temperatures explored here. As Zr content and deposition temperature a...

Characteristics of atomic-layer-deposited thin HfxZr1−xO2 gate dielectrics

Elevated source drain (ESD) structure in deep submicron metal oxide semiconductor field effect transistors (MOSFETs) can help reduce parasitic series resistance and simultaneously achieve shallow contacting junctions to minimize short channel effects A self-aligned ESD structure in conventional complimentary metal–oxide–semiconductor processing can be achieved using silicon selective epitaxial growth (SEG) A robust low thermal budget high quality SEG process using a commercial rapid thermal chemical vapor deposition reactor for ESD formation has been demonstrated The preclean sequence prior to SEG is the key to achieve facet-free epitaxy Low line-to-line leakage confirms the high selectivity to nitride and oxide The growth on exposed polysilicon (poly) gates leads to gate linewidth widening and lower gate sheet resistance ESD parametric data suggest that the well doping needs to be optimized to counter the slight increase in n+-p diode leakage Capacitance–voltage simulations indicate that the gate 

S. B. Samavedam

Papers

Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics

Relaxation of strained Si layers grown on SiGe buffers

Characteristics of atomic-layer-deposited thin HfxZr1−xO2 gate dielectrics

Elevated source drain devices using silicon selective epitaxial growth

Optimization of Hafnium Zirconate (HfZrOx) Gate Dielectric for Device Performance and Reliability