Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

/pdf/wide-band-cmos-low-noise-amplifier-exploiting-thermal-noise-1fma6iskl0.pdf

Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

In this paper, a basic cell for low-power and/or low-voltage operation is identified. It is evidenced how different versions of this cell, coined as "flipped voltage follower (FVF)" have been used in the past for many applications. A detailed classification of basic topologies derived from the FVF is given. In addition, a comprehensive list of recently proposed low-voltage/low-power CMOS circuits based on the FVF is given. Although the paper has a tutorial taste, some new applications of the FVF are also presented and supported by a set of simulated and experimental results. Finally, a design example showing the application of the FVF to build systems based on translinear loops is described which shows the potential of this cell for the design of high-performance low-power/low-voltage analog and mixed-signal circuits.

The flipped voltage follower: a useful cell for low-voltage low-power circuit design

An ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-mum CMOS process, the IC prototype achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8-V supply and occupies an area of only 0.59 mm2

A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

/pdf/a-capacitor-cross-coupled-common-gate-low-noise-amplifier-1xr0i2hjgj.pdf

A capacitor cross-coupled common-gate low-noise amplifier

Inductive-peaking-based bandwidth extension techniques for CMOS amplifiers in wireless and wireline applications are presented. To overcome the conventional limits on bandwidth extension ratios, these techniques augment inductive peaking using capacitive splitting and magnetic coupling. It is shown that a critical design constraint for optimum bandwidth extension is the ratio of the drain capacitance of the driver transistor to the load capacitance. This, in turn, recommends the use of different techniques for different capacitance ratios. Prototype wideband amplifiers in 0.18-mum CMOS are presented that achieve a measured bandwidth extension ratio up to 4.1 and simultaneously maintain high gain (>12 dB) in a single stage. Even higher enhancement ratios are shown through the introduction of a modified series-peaking technique combined with staggering techniques. Ultra-wideband low-noise amplifiers in 0.18-mum CMOS are presented that exhibit bandwidth extension ratios up to 4.9

Bandwidth Extension Techniques for CMOS Amplifiers

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G/sub m/ feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-/spl mu/m CMOS process and is tested using a /spl plusmn/1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58/spl deg/ of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm/sup 2/. Step response shows that the op amp is stable.

Multistage amplifier topologies with nested G/sub m/-C compensation

We report an approach to improve the noise performance of RF low noise amplifiers (LNAs) and down-conversion mixers. The technique we described here is based on capacitive cross-coupling across the two sides of a differential input stage. A LNA and mixer have been implemented in 0.5µ CMOS process to demonstrate the viability of this technique. The measurements show that the LNA achieves 3.0dB noise figure and 12.2 dB voltage gain (optimized for the maximum power transfer), and the mixer has 5.2dB DSB noise figure and 13.2 dB voltage conversion gain. Both LNA and mixer operate at 2.7V voltage supply and consume 27mW and 8.1mW power, respectively.

/pdf/using-capacitive-cross-coupling-technique-in-rf-low-noise-3ymdoplrn8.pdf

Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design

This paper presents a simple class AB buffer which is suitable for low-voltage (1.5 V) applications. The proposed buffer uses an adaptive load to reduce the sensitivity of the quiescent current to the process variation. The main feature of this scheme is its simplicity. The circuit was fabricated in a 2.0 /spl mu/m digital CMOS process. Experimental results demonstrate that the buffer can operate with a supply voltage below 2 V, and it has the capability to drive small resistive loads.

Low-voltage class AB buffers with quiescent current control

The inherent capability of floating-gate MOS transistors, of performing addition of weighted input signals, can be exploited to realize single D/A converter architectures. A single floating-gate MOS device can be used as a D/A converter. Its precision for large number of bits is, however, poor. A parallel D/A architecture using floating-gate MOS transistors is proposed. This architecture is very simple but provides better precision than the single transistor D/A converter. An 8-bit D/A converter is presented and simulated to demonstrate the functionality.

S.H.K. Embabi

Papers

A capacitor cross-coupled common-gate low-noise amplifier

Multistage amplifier topologies with nested G/sub m/-C compensation

Using capacitive cross-coupling technique in RF low noise amplifiers and down-conversion mixer design

Low-voltage class AB buffers with quiescent current control

A floating-gate MOSFET D/A converter