Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

Hot-electron-induced MOSFET degradation&#8212;Model, monitor, and improvement

The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.

Flash memory cells-an overview

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

Avalanche-induced breakdown mechanisms for short-channel MOSFET's are discussed. A simple analytical model that combines the effects due to the ohmic drop caused by the substrate current and the positive feedback effect of the substrate lateral bipolar transistor is proposed. It is shown that two conditions must be satisfied before breakdown will occur. One is the emission of minority carriers into the substrate from the source junction, the other is sufficient avalanche multiplication to cause significant positive feedback. Analytical theory has been developed with the use of a published model for short-channel MOSFET's. The calculated breakdown characteristics agree well with experiments for a wide range of processing parameters and geometries.

An analytical breakdown model for short-channel MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.

Correlation between substrate and gate currents in MOSFET's

The presence of oxide/semiconductor interface trapped charge (ITC) and its spatial nonuniformity can adversely affect the operation of MOSFETs. The advanced techniques which are used to fabricate circuits with devices of submicrometer geometries make use of radiation which can alter the number and charge state of these defects  and modify the device operating characteristics. The traditional methods of measurement of ITC involve the use of large MOS capacitors to obtain accurate values for ITC. Since the processing history of these structures can differ substantially from the processing of typical MOSFETs, the values of ITC obtained from capacitors are often significantly different from  the values measured on MOSFETs. Three direct methods for the measurement of ITC using short-channel MOSFETs have been evaluated: 1) the weak inversion method [l], 2) the use of the slope of the subthreshold current [21 and 3) the charge pump method Dl. The weak inversion  method breaks down for  short-channel  transistors because the  on-set of saturation in short-channel transistors is not clearly defined. The use of the slope of the subthreshold  current is obscured ' by drain  induced  subthreshold current  components. The charge pump method makes use of current produced by repetitively pulsing the channel of a MOSEET from  accumulation  to  inversion and measuring the resulting  current produced in  an  external circuit. When the pulse inverts the substrate, carriers from the source and drain  form the substrate inversion layer. These carriers are trapped in the interface  de e ts.  During accumulation,  it is assumed  that all the excess mobile carriers in the inversion layer return to the source  and drain and  the charge pump current is due to the exchange of charge between the interface traps and the bulk silicon. In  short-channel  devices,  this assumption is met. Only the channel width, length,  and  measurement  frequency  are required to calculate the ITC density from the charge  pump  current. Using detailed two-dimensional calculations of the channel inversion shape in short-channel transistors, we have shown that the channel  length required  for  this measurement can be obtained, in a self aligned process, from the gate length. Using an automated parametric test  system, the spatial variation of ITC across wafers was measured on pand nchannel MOSFETs fabricated using a self aligned CMOS bulk process. The mean value of ITC  for the p-channel device (6.6 X 10" cmV2) was twice the mean for the n-channel device (3.3 X 10" cm-2). This suggest that boron contamination from the source/drain  in the p-channel device may contribute to the difference in ITC.

S. Tam

Papers

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

An analytical breakdown model for short-channel MOSFET's

Correlation between substrate and gate currents in MOSFET's

VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs

S. Tam

Papers

Hot-electron-induced MOSFET degradation&#8212;Model, monitor, and improvement

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

An analytical breakdown model for short-channel MOSFET's

Correlation between substrate and gate currents in MOSFET's

VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement