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Showing papers by "Samit K. Ray published in 1997"


Journal ArticleDOI
TL;DR: In this paper, the electrical properties of grown oxide have been characterized using a metal-oxide-semiconductor structure, and the oxide on strained-Si samples has exhibited hole trapping behavior and moderately low interface state generation on constant current stressing.
Abstract: Microwave plasma oxidation (below 200 °C) of strained Si on relaxed Si1−xGex buffer layers in N2O ambient is reported. The electrical properties of grown oxide have been characterized using a metal-oxide-semiconductor structure. Fixed oxide charge density and mid-gap interface state density are found to be 6×1010 cm−2 and 1.2×1011 cm−2 eV−1, respectively. The oxide on strained-Si samples has exhibited hole trapping behavior and moderately low interface state generation on constant current stressing.

16 citations


Journal ArticleDOI
TL;DR: In this article, the state-of-the-art silicon-germanium heteroepitaxy techniques are reviewed, including the use of Gas Source Molecular Beam Epitaxy (GSMBE) on p-Si.
Abstract: State-of-the-art silicon-germanium heteroepitaxy techniques are reviewed. Strained Si1–x Gex epitaxial films have been grown by Gas Source Molecular Beam Epitaxy (GSMBE) on p-Si. The films have bee...

16 citations


Journal ArticleDOI
TL;DR: In this paper, a strain-compensated growth of Si 1− x − y Ge x C y with a wide range of composition was shown to be possible in the present RTCVD system at temperatures of approximately 700 °C.

15 citations


Journal ArticleDOI
TL;DR: In this paper, the electrical properties of grown oxide have been characterized and compared with thermally grown oxides using a metal-oxide semiconductor structure, and the accumulation of holes in the buried Si1−xGex layer, due to the type-II band offset, has been observed.
Abstract: Electron cyclotron resonance plasma oxidation of strained Si on relaxed Si1−xGex buffer layers in O2 ambient at room temperature is reported. The electrical properties of grown oxide have been characterized and compared with thermally grown oxides using a metal-oxide semiconductor structure. At a low field, the accumulation of holes in the buried Si1−xGex layer, due to the type-II band offset, has been observed. The experimental results from thermally grown oxides have been compared with the simulation results obtained using a heterostructure Poisson solver.

15 citations


Journal ArticleDOI
TL;DR: The Schottky barrier height and ideality factor of Pt on p-type strained Si (grown on a graded relaxed Si0.82Ge0.18 buffer layer) have been investigated in the temperature range (90 −150 K) using the current-voltage characteristics and are found to be temperature dependent as discussed by the authors.
Abstract: The Schottky barrier height and ideality factor of Pt on p-type strained Si (grown on a graded relaxed Si0.82Ge0.18 buffer layer) have been investigated in the temperature range (90–150 K) using the current-voltage characteristics and are found to be temperature dependent. While the ideality factor decreases with an increase in temperature, the barrier height increases. Simulation based on a drift-diffusion emission model has been used to explain the experimental results.

13 citations


Journal ArticleDOI
TL;DR: The Schottky barrier height and ideality factor of p-type strained-Si (grown on a graded relaxed Si0.82Ge0.18 buffer layer) were investigated in the temperature range 200-300 K using the currentvoltage (I-V) characteristics and were found to be temperature dependent.
Abstract: The Schottky barrier height and ideality factor of Ti on p-type strained-Si (grown on a graded relaxed Si0.82Ge0.18 buffer layer) were investigated in the temperature range 200–300 K using the current-voltage (I-V) characteristics and were found to be temperature dependent. While the ideality factor decreases with an increase in temperature, the barrier height increases.

7 citations


Proceedings ArticleDOI
23 Jun 1997
TL;DR: In this article, the authors proposed vertical Si/sub 1-x/Ge/sub x/Si PMOS and Si NMOS transistors and demonstrated a 100% increase of drive current in a vertical SiGe PMOS device, and the first experimental evidence of the enhancement of out-of-plane hole mobility in vertical PMOSFET.
Abstract: CMOS devices are being scaled for density and speed. However, scaling gate length is impeded by lithographic technology and scaling device width is limited by low hole mobility in PMOS transistors. In vertical MOS transistors, however, lithography does not limit the channel length. Current drive in PMOS devices may also be increased by use of a SiGe channel. In fact, the hole mobility in strained SiGe normal to the growth plane is predicted to be significantly larger than in its unstrained counterpart. Therefore, we propose vertical Si/sub 1-x/Ge/sub x//Si PMOS and Si NMOS transistors and demonstrate (1) 100% increase of drive current in a vertical SiGe PMOS device, (2) the first experimental evidence of the enhancement of out-of-plane hole mobility in a vertical PMOSFET, and (3) experimental results for vertical NMOS devices, thus exhibiting the promise of vertical SiGe/Si CMOS.

4 citations


Journal ArticleDOI
TL;DR: In this article, the integration issues of SiGe strained layers in Si-technology-based integrated circuits are addressed and the present status of the silicon dioxide formation on SiGe films is reviewed.
Abstract: Integration issues of SiGe strained layers in Si-technology-based integrated circuits are addressed. The present status of the silicon dioxide formation on SiGe films is reviewed. Results of our studies on the low temperature (150–200°C) growth of ultrathin oxides using microwave plasma (in both O2 and N2O ambient), compositional analysis, electrical characterization and interfacial properties of the oxides are presented. Hole confinement in a Gas Source Molecular Beam Epitaxy (GSMBE) grown Si0.74Ge0.26/Si quantum well on silicon using (i) computer simulation and (ii) C-V measurements are also demonstrated.

2 citations


Proceedings ArticleDOI
27 Aug 1997
TL;DR: In this article, the authors present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation, which was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices.
Abstract: As channel lengths shrink continuously to smaller dimensions in order to improve performance and packing density, lithography, isolation, power supply and short channel effects have proved to be major limitations. Recently vertical MOSFETs (VMOS), also known as surround gate transistors, or 3-D side- wall transistors have been shown to overcome these process limitations. In this paper, we review the various VMOS technologies and applications and compare the performance of these devices to planar devices. We also present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation. The Ge was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobilities in Si.

Journal ArticleDOI
TL;DR: The Schottky barrier height of Ti on p-type Si1-xGex/Si and Si and Si have been investigated in the temperature range 110-250 K using the current voltage technique as mentioned in this paper.
Abstract: The Schottky barrier height of Ti on p-type Si1–xGex/Si and Si have been investigated-in the temperature range 110–250 K using the current voltage technique. Rutherford Backscattering Spectroscopy ...