https://iopscience.iop.org/article/10.35848/1882-0786/abc787/pdf

Defect engineering in SiC technology for high-voltage power devices

This letter reports a new 900 V 4H-SiC JBSFET containing an MOSFET with an integrated JBS diode in the center area of the chip. Both MOSFET and JBS diode structures utilize the same edge termination structure,which results in 30% reduction in SiC wafer area consumption in case of 10 A rating device. In order to form a Schottky contact for the JBS diode as well as ohmic contacts for n+ source and p+ body of the MOSFET,a simple metal process flow has been newly developed. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). The proposed JBSFET was successfully fabricated using a nine-mask on 6-in 4H-SiC wafers.

Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme

SiC-MOSFETs provide superior performance for next generation power electronics systems. High threshold voltage 600 V SiC-MOSFETs were realized utilizing a reoxidation process, which drastically improves a tradeoff between an ON-resistance and a threshold voltage. Low-loss SiC-MOSFETs with a 1200 V/100-A rating have been developed. Using the developed SiC-MOSFETs, 1200 V/800-A high-power full SiC module with an ON-resistance as low as 2.9 m $\Omega $ at 150 °C was successfully fabricated. The high-power module markedly reduces power loss especially at high carrier frequency. Large-area 3300 V SiC-MOSFETs with an ON-resistance of 52 m $\Omega $ at 175 °C exhibit an adequate reverse bias safe operating area and 3300 V SiC-MOSFETs screened by applying a body diode current stress show stable characteristics under a continuous current through their body diode for 1000 h.

Characteristics of 600, 1200, and 3300 V Planar SiC-MOSFETs for Energy Conversion Applications

We investigated the dependency of minority carrier lifetimes on the nitrogen concentration, temperature, and the injected carrier concentration for highly nitrogen-doped 4H-SiC epilayers. The minority carrier lifetimes greatly shortened when the nitrogen concentration exceeded 1018 cm−3 through enhancing direct band-to-band and Auger recombination and showed a slight variation in the temperature range from room temperature (RT) to 250 °C. The epilayer with a nitrogen concentration of 9.3 × 1018 cm−3 exhibited a very short minority carrier lifetime of 38 ns at RT and 43 ns at 250 °C. The short minority carrier lifetimes of the highly nitrogen-doped epilayer were confirmed to maintain the values even after the subsequent annealing of 1700 °C. 4H-SiC PiN diodes were fabricated by depositing a highly nitrogen-doped epilayer as a “recombination enhancing layer” between an n− drift layer free from basal plane dislocations and the substrate. The PiN diodes showed no formation of stacking faults and no increase in forward voltage during current conduction of 600 A/cm2 (DC), demonstrating that a highly nitrogen-doped buffer layer with a short minority carrier lifetime successfully suppresses the “bipolar degradation” phenomenon.

Short minority carrier lifetimes in highly nitrogen-doped 4H-SiC epilayers for suppression of the stacking fault formation in PiN diodes

For higher-voltage SiC modules, larger SBD chips are required as free-wheel diodes to suppress current conduction of the body diodes of MOSFETs, which causes bipolar degradation following the expansion of stacking faults. By embedding an SBD into each unit cell of a 6.5 kV SiC-MOSFET, we achieved, without using external SBDs, a high-voltage switching device that is free from bipolar degradation. Expansion of the active area by embedding SBDs is only 10% or less, whereas the active area of external SBDs can be over three times larger than that of the coupled MOSFET. The fabricated 6.5 kV SBD-embedded SiC-MOSFETs show sufficiently high breakdown voltages, low specific on-resistances, no bipolar degradation, and good reliability.

6.5 kV schottky-barrier-diode-embedded SiC-MOSFET for compact full-unipolar module

We evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocations (TEDs) under the current stress to the pn devices and analyzed the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, Focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques. It was found that the formation of SFs occurs upon the current stress levels of 400 A/cm2 where the diode area is not including BPDs in the drift layer after the high current stress, and the high current stress increases the SFs expansion density. It was also found the dependence of the junction temperature. The estimated activation energy for the expansion of SFs is Ea = 0.46 eV. The SF extends from the conversion point of the BPD into the TED within buffer layer. Even though BPDs converted into TEDs within the high doped buffer layer, SFs expand under high current stress.

Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress

External Schottky barrier diodes (SBD) are generally used to suppress the conduction of the body diode of MOSFET. A large external SBD is required for a high voltage module because of its high specific resistance, while the forward voltage of SBD should be kept smaller than the built-in potential of the body diode. Embedding SBD into MOSFET with short cycle length increases maximum source-drain voltage where body diode remains inactive, resulting in high current density of SBD current. We propose a MOSFET structure where an SBD is embedded into each unit cell and an additional doping is applied, which allows high current density in reverse operation without any activation of body diode. The proposed MOSFET was successfully fabricated and much higher reverse current density was demonstrated compared to the external SBD. We can expect to reduce total chip size of high voltage modules using the proposed MOSFET embedding SBD.

Demonstration of SiC-MOSFET embedding Schottky barrier diode for inactivation of parasitic body diode

In order to achieve cost reduction or shrinkage of power devices, an internal body diode, which forms in a MOSFET parasitically, can be designed as a free-wheeling diode in substitution for an external Schottky barrier diode (SBD). However, in a SiC p-i-n diode, forward current stress causes reliability degradation due to expansion of the electron-hole recombination-induced stacking faults. Applying the process optimization of the epitaxial layer for the reduction of recombination-induced stacking faults and the body diode screening method to 3.3 kV SiC-MOSFETs, we obtained more stable devices under forward current operation.

Development of 3.3 kV SiC-MOSFET: Suppression of Forward Voltage Degradation of the Body Diode

We evaluate the velocity of stacking faults (SFs) expansion under various current and temperature levels on the pn diodes by electroluminescence (EL) observation in situ. The driving force of the SFs expansion is analyzed on the basis of the experimental results. The velocity of the SFs expansion increases in proportional to the current density at the every junction temperature levels. The activation energy for the velocity of the SFs expansion is estimated.

Driving Force of Stacking Fault Expansion in 4H-SiC PN Diode by In Situ Electroluminescence Imaging

PROBLEM TO BE SOLVED: To provide a silicon carbide chip, a silicon carbide wafer, a test method for a silicon carbide chip, and a test method for a silicon carbide wafer, to which a current conduction test can be applied even when a chip has a large area.SOLUTION: A silicon carbide chip 4 includes a product chip region 1 in which a silicon carbide semiconductor element performing an actual action is crated, and a PN diode 3 which is disposed around the product chip region 1 and which is not involved in an actual action of a smaller area than the product chip region 1.

Shigehisa Yamamoto

Papers

Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress

Demonstration of SiC-MOSFET embedding Schottky barrier diode for inactivation of parasitic body diode

Development of 3.3 kV SiC-MOSFET: Suppression of Forward Voltage Degradation of the Body Diode

Driving Force of Stacking Fault Expansion in 4H-SiC PN Diode by In Situ Electroluminescence Imaging

Silicon carbide chip, silicon carbide wafer, test method for silicon carbide chip, and test method for silicon carbide wafer