S
Shoichi Masui
Researcher at Tohoku University
Publications - 34
Citations - 1556
Shoichi Masui is an academic researcher from Tohoku University. The author has contributed to research in topics: Integrated circuit & Non-volatile memory. The author has an hindex of 9, co-authored 30 publications receiving 1529 citations. Previous affiliations of Shoichi Masui include Stanford University & Fujitsu.
Papers
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Journal ArticleDOI
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
TL;DR: In this paper, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. But the authors did not consider the effect of the layout geometry of the substrate.
Journal Article
Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits
TL;DR: In this article, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. And the authors showed that in such cases the substrate noise is highly dependent on layout geometry.
Patent
Programmable logic device with ferroelectric configuration memories
TL;DR: In this paper, a programmable logic device with ferroelectric configuration memories storing multiple configuration data sets is presented, which can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories.
Journal ArticleDOI
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g m / I D Lookup Table Methodology
TL;DR: The design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS is proposed, and the possibility of applying this design methodology as a technology migration tool is explored.
Patent
Programmable logical device
Shoichi Masui,Kenji Mukoda,Tsuzumi Ninomiya,Michiya Oura,Wataru Yokozeki,鼓 二野宮,健二 向田,道也 大浦,昇一 桝井,亘 横関 +9 more
TL;DR: In this paper, a programmable logical device which can realize an inexpensive board system by decreasing the number of logical gates per unit area is presented. But it is not shown how to use the plurality of pieces of configuration information while switching and no extra nonvolatile memory is required externally.