As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise.

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Noise in deep submicron digital design

A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Semiconductor memory device and method of operating the same

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effectiveness is demonstrated. A simple RC model has been developed to allow a deep understanding of these phenomena as well as to simplify future studies of more complex systems. The superiority of high-resistivity SIMOX substrates over standard SOI and bulk is finally demonstrated.

Substrate crosstalk reduction using SOI technology

This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented.

Modeling and analysis of substrate coupling in integrated circuits

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.

Programmable logic device with ferroelectric configuration memories

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125MS/s pipeline A/D converter implemented in a 0.18µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g m / I D Lookup Table Methodology

PROBLEM TO BE SOLVED: To obtain a programmable logical device which can realize an inexpensive board system by decreasing the number of logical gates per unit area. SOLUTION: A logical block 1 capable of implementing various logical functions, programmable wiring 2 capable of altering the connection state, and a programmable I/O block 3 capable of altering the I/O state are provided with ferroelectric memories 4, 5 and 6 for storing configuration information defining the operation thereof. A plurality of pieces of configuration information are stored in each ferroelectric memory 4, 5, 6 and an information selecting means 7, 8, 9 selects an arbitrary one. The number of logical gates can be substantially increased by using the plurality of pieces of configuration information while switching and an inexpensive board system can be realized because no extra nonvolatile memory is required externally. COPYRIGHT: (C)2003,JPO

Shoichi Masui

Papers

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Programmable logic device with ferroelectric configuration memories

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g m / I D Lookup Table Methodology

Programmable logical device