Showing papers by "Souvik Mahapatra published in 2006"

On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

Abstract: A common framework for interface-trap (NIT) generation involving broken equivSi-H and equivSi-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress. Holes (from inversion layer for pMOSFET NBTI, from channel due to impact ionization, and from gate poly due to anode-hole injection or valence-band hole tunneling for nMOSFET HCI) break equivSi-H bonds, whose time evolution is governed by either one-dimensional (NBTI or FN) or two-dimensional (HCI) reaction-diffusion models. Hot holes break equivSi-O bonds during both FN and HCI stress. Power-law time exponent of NIT during stress and recovery of NIT after stress are governed by relative contribution of broken equivSi-H and equivSi-O bonds (determined by cold- and hot-hole densities) and have important implications for lifetime prediction under NBTI, FN, and HCI stress conditions

Gate Leakage vs. NBTI in Plasma Nitrided Oxides: Characterization, Physical Principles, and Optimization

Abstract: Since nitrided oxides improve gate leakage at the expense of NBTI, one must optimize nitrogen concentration in oxinitride samples for reliable performance and reduced power dissipation. Here, we analyze wide range of NBTI stress data to develop a predictive model for gate leakage and first self-consistent model for field acceleration within R-D framework. This model anticipates a novel design diagram for co-optimization of leakage and NBTI for arbitrary nitrogen concentration and effective oxide thickness.

Comprehensive Simulation of Program, Erase and Retention in Charge Trapping Flash Memories

Abstract: A simulator is developed for SONOS Flash memories to predict Program (P), Erase (E) and Retention (R) behavior under uniform 1D operation. It provides insight on the impact of trap parameters on P, E and R and can be used to optimize memory stacks.

Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress

Abstract: Interface trap (N/sub IT/) generation and recovery due to broken /spl equiv/Si-H bonds at the Si/SiO/sub 2/ interface is studied during and after hot carrier injection (HCI) stress and verified by a two-dimensional reaction-diffusion model. N/sub IT/ generation and recovery characteristics do not correlate with channel hot electron (HE) density distribution (verified by Monte Carlo simulations). Anode hole injection, which is triggered by HE injection into the gate poly, and valence band hole tunneling, which is triggered for thinner oxides, must be invoked to properly explain experimental results. The observed hole-induced, not electron-induced, breaking of /spl equiv/Si-H bonds during HCI stress is also consistent with that for negative bias temperature instability stress.

Interface-Trap Driven NBTI for Ultrathin (EOT~12Å) Plasma and Thermal Nitrided Oxynitrides

Abstract: Negative bias temperature instability (NBTI) is studied in ultrathin Si oxynitride (SiON) films made by thermal (TNO) and plasma (PNO) processes. Threshold voltage degradation (DeltaVT) and recovery during and after NBTI stress are explained by generation and recovery of interface traps (DeltaNIT)

Endurance and Retention Characteristics of SONOS EEPROMs Operated using BTBT Induced Hot Hole Erase

Abstract: Endurance and retention of SONOS EEPROMs operated using channel hot electron injection (CHEI) and band-to-band tunneling (BTBT) induced hot hole injection (HHI) are studied. Cycling window closure is improved by optimizing erase bias, and its effect on cell degradation is studied. The retention loss in program state is studied under different erase conditions and correlated to cell degradation caused by HHI.

On the generation and recovery of hot carrier induced interface traps: a critical examination of the 2-D R-D model

Abstract: The generation and recovery of interface traps (N/sub IT/) during and after hot carrier injection stress is evaluated by the recently proposed two-dimensional (2-D) reaction diffusion (R-D) model. The power law time exponent (n) of N/sub IT/ generation as well as the magnitude of fractional and absolute recovery after the stress cannot be fully explained by considering only the spatial extent of broken /spl equiv/Si-H bonds, as is done by 2-D R-D model. Additional contribution due to broken /spl equiv/Si-O bonds also plays a major role in determining the overall N/sub IT/ generation and recovery behavior.

Using soft secondary electron programming to reduce drain disturb in floating-gate NOR flash EEPROMs

Abstract: A novel concept of soft secondary electron programming (SSEP) is introduced and shown to be a promising programming scheme for scaled NOR flash electrically erasable programmable read-only memories. Although the mechanism is similar to that of the channel-initiated secondary electron (CHISEL) programming, SSEP uses an "optimum" substrate bias that results in a lower drain disturb compared with both channel hot electron (CHE) and conventional CHISEL programming schemes. The concept behind minimizing drain disturb is discussed. SSEP is shown to give faster programming and lower disturb than CHE at all operating conditions, as well as better program/disturb margin compared with conventional CHISEL programming at similar program speed or disturb time. The effect of repeated program/erase cycling using SSEP is compared against CHE and CHISEL cycling.