Showing papers by "Souvik Mahapatra published in 2014"

Universality of NBTI - From devices to circuits and products

Abstract: This paper showcases the universality of NBTI and its dependencies on time, bias, temperature, AC frequency and pulse duty cycle across different process integration schemes used in the industry and technology nodes. Strong correlation has been established between device, circuit, and product degradation. Different aspects of variability and variable NBTI in small area devices have been discussed. Features that are important from an industrial perspective are highlighted. Any NBTI model should address these aspects to be considered relevant.

Trap Generation in IL and HK layers during BTI / TDDB stress in scaled HKMG N and P MOSFETs

Abstract: Independent Trap Generation (TG) monitors such as DCIV and SILC have been used during NBTI, PBTI (and TDDB) stress in differently processed HKMG devices. TG from DCIV for NBTI is attributed to Si/IL and IL/HK interfaces; TG from DCIV for PBTI to IL/HK interface but at similar energy location as NBTI. TG from DCIV shows similar stress bias (V G,STR ), time (t STR ) and temperature (T) dependence for NBTI and PBTI, while TG for PBTI from SILC shows very different dependence as it likely scans TG at different spatial and energetic locations. TG contribution to V T shift (ΔV T ) is compared to ΔV T from ultra-fast measurements. A compact model is used to predict overall BTI ΔV T considering uncorrelated contributions from independently measured TG and trapping (TP) in pre-existing and generated bulk traps. Impact of IL scaling on BTI and its underlying subcomponents are studied. Physical origins of different TG and TP processes have been identified using Density Functional Theory (DFT) simulations.

A comprehensive DC/AC model for ultra-fast NBTI in deep EOT scaled HKMG p-MOSFETs

Abstract: DC and AC NBTI in deep EOT scaled HKMG p-MOSFETs with different IL (scaled to sub 2A) are measured by UF-MSM method with 10μs delay. A model with interface trap generation (ΔV IT-IL ) at Si/IL interface, hole trapping (ΔV HT ) in IL bulk and trap generation (ΔV IT-HK ) linked to H passivated Oxygen vacancy (Ov-H) defects in IL/HK interfacial transition layer has been proposed. The existence of Ov defects and their energy levels are verified using DFT simulation. The model can successfully predict V T shift (ΔV T ) during and after DC stress, dependence on pulse duty cycle (PDC) and frequency (f) for AC stress, and gate insulator process dependence with consistent set of parameters. Impact of EOT scaling on DC and AC NBTI is studied, and end-of-life degradation has been estimated.

A Detailed Study of Gate Insulator Process Dependence of NBTI Using a Compact Model

Abstract: Process impact of negative bias temperature instability (NBTI) is studied in silicon oxynitride (SiON) and high- k metal gate (HKMG) p-MOSFETs. An analytical compact model is used to predict long time degradation. NBTI is shown to be governed by the generation of interface and bulk oxide traps and hole trapping in preexisting traps that are mutually uncorrelated. Experimental evidences are provided to independently verify underlying components. Model parameters are extracted; only a few process-dependent parameters are needed to predict the experimental data from wide range of SiON and HKMG p-MOSFETs at various stress bias and temperature. Similarity between SiON and HKMG devices is highlighted.

DC / AC BTI Variability of SRAM Circuits Simulated Using a Physics-Based Compact Model

Abstract: A physics-based compact model has been developed to predict DC and AC Bias Temperature Instability (BTI) induced threshold voltage shift (ΔV T ) in HKMG MOSFETs. For Negative BTI (NBTI) in p-MOSFETs, the model uses Si/IL interface trap generation (ΔV IT-IL ) and hole trapping in IL bulk (ΔV HT-IL ). For Positive BTI (PBTI) in n-MOSFETs, it uses IL/HK interface trap generation (ΔV IT-HK ) and electron trapping in HK bulk (ΔV ET-HK ). The model framework has been extended to generate device level stochastic ΔV T distributions, and eventually V T distributions by taking time zero variability into account. V T distributions with stress time for DC and AC stress, and for different duty cycles for AC stress are investigated. The resulting impact on 6T and 8T SRAM cells is studied for read as well as first and second write operations after different stress time and activity conditions, and long time failure probabilities are obtained.

A Comprehensive Modeling Framework for DC and AC NBTI

Abstract: This chapter presents a comprehensive modeling framework to explain DC and AC NBTI experiments. The framework consists of uncorrelated contribution from interface trap generation, along with hole trapping in process-related preexisting and stress-induced generated bulk insulator traps. A wide range of experimental data, such as time evolution of degradation during and after DC stress, very long-time stress experiments, AC degradation as a function of pulse duty cycle and frequency, and measurement speed dependence of DC and AC NBTI, can be successfully explained for devices having wide range of gate insulator processes. Model equations and parameters have been listed.

FEOL and BEOL Process Dependence of NBTI

Abstract: This chapter reviews different transistor processes that influence NBTI degradation. Effect of gate oxidation under dry and wet ambient, incorporation of nitrogen and fluorine, compressive stress, type of source-drain dopant atoms, hydrogen and deuterium post metallization anneal, use of different barrier metals, inter-metal dielectrics, and cap layers, as well as antenna charging are briefly reviewed. Due to its technological importance, a detailed review of nitrogen incorporation effect on NBTI, measured using ultrafast measurement method, is also done. The impact of nitrogen distribution profile in the gate insulator stack on NBTI degradation magnitude and parameters are studied in both SiON and HKMG devices. Key process dependent results are summarized.

Modeling of stochastic BTI in small area devices and its impact on SRAM performance

Abstract: A comprehensive framework is developed to simulate device-level variability due to process variations and Bias Temperature Instability (BTI), and study the impact on circuits such as the SRAM cell. Stochastic simulation approach consisting of the stochastic Reaction Diffusion (RD) model for interface trap generation and stochastic two energy well model for charging of pre-existing bulk traps along with either simple exponential impact assumption or complete 3D TCAD simulation, is used to generate threshold voltage and threshold voltage shift distributions. A compact model approach to generate the threshold voltage distributions from the mean compact model through a procedure that exploits experimental relationship between mean and variance of threshold voltage shift distribution is described. The impact of device-level variability on the 6T-SRAM cell read and write operations is investigated.