There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Intermittently powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number generation. Our measurements show that power-up of SRAM produces a physical fingerprint. We propose a system of fingerprint extraction and random numbers in SRAM (FERNS) that harvests static identity and randomness from existing volatile CMOS memory without requiring any dedicated circuitry. The identity results from manufacture-time physically random device threshold voltage mismatch, and the random numbers result from runtime physically random noise. We use experimental data from high-performance SRAM chips and the embedded SRAM of the WISP UHF RFID tag to validate the principles behind FERNS. For the SRAM chip, we demonstrate that 8-byte fingerprints can uniquely identify circuits among a population of 5,120 instances and extrapolate that 24-byte fingerprints would uniquely identify all instances ever produced. Using a smaller population, we demonstrate similar identifying ability from the embedded SRAM. In addition to identification, we show that SRAM fingerprints capture noise, enabling true random number generation. We demonstrate that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. We demonstrate this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by negative bias temperature instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worst-case speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.

Circuit Failure Prediction and Its Application to Transistor Aging

A comprehensive framework is developed to simulate device-level variability due to process variations and Bias Temperature Instability (BTI), and study the impact on circuits such as the SRAM cell. Stochastic simulation approach consisting of the stochastic Reaction Diffusion (RD) model for interface trap generation and stochastic two energy well model for charging of pre-existing bulk traps along with either simple exponential impact assumption or complete 3D TCAD simulation, is used to generate threshold voltage and threshold voltage shift distributions. A compact model approach to generate the threshold voltage distributions from the mean compact model through a procedure that exploits experimental relationship between mean and variance of threshold voltage shift distribution is described. The impact of device-level variability on the 6T-SRAM cell read and write operations is investigated.

Modeling of stochastic BTI in small area devices and its impact on SRAM performance

BAT Framework Modeling of Gate First HKMG Si-Capped SiGe Channel MOSFETs

In this chapter, the BAT framework presented in Chap. 4 through Chap. 6 is used to analyze and model the measured NBTI time kinetics during and after AC stress. Modeling is done on ultra-fast measured data at different stress modes (A and B), pulse duty cycle, frequency, and pulse low bias. Several features of AC kinetics are shown to be universal across Gate First HKMG p-MOSFETs and RMG HKMG SOI p-FinFETs having Silicon channel and RMG HKMG bulk p-FinFETs having Silicon Germanium channel. The controversy regarding the frequency dependence or independence of AC NBTI stress is analyzed and explained.

BAT Framework Modeling of AC NBTI: Stress Mode, Duty Cycle and Frequency

In this chapter, the p-MOSFET parametric drift during and after DC NBTI stress is discussed. Data from devices having different architectures (bulk and FDSOI planar, FinFET, and GAA-SNS FET) are shown. The influences of key technological processes, such as Nitrogen content in the gate insulator, Germanium content in the channel, and mechanical stress in the channel due to changes in the transistor layout or device dimensions are discussed. The variability in parametric drift associated with small area devices is also discussed.

Souvik Mahapatra

Papers

Modeling of stochastic BTI in small area devices and its impact on SRAM performance

BAT Framework Modeling of Gate First HKMG Si-Capped SiGe Channel MOSFETs

BAT Framework Modeling of AC NBTI: Stress Mode, Duty Cycle and Frequency

Device Architecture, Material and Process Dependencies of NBTI Parametric Drift

BAT Framework Modeling of Gate First HKMG Si Channel MOSFETs