There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Intermittently powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number generation. Our measurements show that power-up of SRAM produces a physical fingerprint. We propose a system of fingerprint extraction and random numbers in SRAM (FERNS) that harvests static identity and randomness from existing volatile CMOS memory without requiring any dedicated circuitry. The identity results from manufacture-time physically random device threshold voltage mismatch, and the random numbers result from runtime physically random noise. We use experimental data from high-performance SRAM chips and the embedded SRAM of the WISP UHF RFID tag to validate the principles behind FERNS. For the SRAM chip, we demonstrate that 8-byte fingerprints can uniquely identify circuits among a population of 5,120 instances and extrapolate that 24-byte fingerprints would uniquely identify all instances ever produced. Using a smaller population, we demonstrate similar identifying ability from the embedded SRAM. In addition to identification, we show that SRAM fingerprints capture noise, enabling true random number generation. We demonstrate that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. We demonstrate this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by negative bias temperature instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worst-case speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.

Circuit Failure Prediction and Its Application to Transistor Aging

A systematic review and comparison of existing charge trapping models in literature is performed. A framework for simulating hole trapping/de-trapping kinetics is established to compute resultant threshold voltage degradation ($\Delta \mathrm{V}_{\mathrm{HT}})$ and capture-emission time constants ($\tau_{C}-\tau_{E}$). The models are analyzed by using data from Negative Bias Temperature Instability (NBTI), Random Telegraph Noise (RTN) and Time Dependent Defect Spectroscopy (TDDS) experiments.

6-3 Benchmarking Charge Trapping Models with NBTI, TDDS and RTN Experiments

Ultrafast measurements (with 10μs delay) are done to characterize the Negative Bias Temperature Instability (NBTI) and Hot Carrier Degradation (HCD) induced threshold voltage shift (ΔVT) in p-channel Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs). A model framework is proposed to estimate the measured ΔVT time kinetics during and after NBTI and HCD stress. The BTI Analysis Tool (BAT) framework is calibrated using pure NBTI data (drain bias, VD, at 0V) across gate bias (VG) and temperature (T) and is subsequently used to estimate the underlying NBTI contribution during and after HCD stress under full VG/VD space in the presence of Self-Heating (SH) effect. The pure HCD kinetics is calculated using an empirical model, with VG, VD and T dependence incorporated via a vertical field enhanced dominant energy model.

Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress

Charge loss mechanisms during Data retention (DR) in GAA 3D NAND devices, Inter-cell charge loss of electrons in the Charge Trap Layer (CTL), and In-cell charge loss of electrons from tunnel oxide are modeled and analyzed using a physics-based Activated Barrier Double Well Thermionic Emission (ABDWT) model. The measured data retention characteristics for Solid Pattern (SP), of various distribution, sigma $(\sigma)$ of the lower tail of the Cell Voltage Distribution (CVD) has been studied and modeled for various temperatures and programming levels (PL). Checkered pattern (CP) measured long-term data retention characteristics at various temperatures and program levels are modeled for both the loss components. 10 years projection is extrapolated across temperature and programing levels.

A Physics-based Model for Long Term Data Retention Characteristics in 3D NAND Flash Memory

The Compact-Physical (Comphy) framework is tested against the experimental Negative Bias Temperature Instability (NBTI) data. A cost-function based optimizer is used for obtaining the parameters of Comphy. The ultrafast (10 μs delay) measured threshold voltage shift (ΔVT) during and after NBTI stress at various stress (VGSTR) and recovery (VGREC) bias, temperature (T) and stress time (tSTR), and mixed AC–DC stress using random VGSTR, VGREC, pulse duty cycle (PCD) and frequency (f) are used to test the model framework. The BTI Analysis Tool (BAT) framework, for which data from previous work is used, and Comphy are compared. 

Souvik Mahapatra

Papers

6-3 Benchmarking Charge Trapping Models with NBTI, TDDS and RTN Experiments

Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress

A Physics-based Model for Long Term Data Retention Characteristics in 3D NAND Flash Memory

Comparative analysis of NBTI modeling frameworks BAT and Comphy

BAT Framework Modeling of RMG HKMG SOI FinFETs