There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Intermittently powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number generation. Our measurements show that power-up of SRAM produces a physical fingerprint. We propose a system of fingerprint extraction and random numbers in SRAM (FERNS) that harvests static identity and randomness from existing volatile CMOS memory without requiring any dedicated circuitry. The identity results from manufacture-time physically random device threshold voltage mismatch, and the random numbers result from runtime physically random noise. We use experimental data from high-performance SRAM chips and the embedded SRAM of the WISP UHF RFID tag to validate the principles behind FERNS. For the SRAM chip, we demonstrate that 8-byte fingerprints can uniquely identify circuits among a population of 5,120 instances and extrapolate that 24-byte fingerprints would uniquely identify all instances ever produced. Using a smaller population, we demonstrate similar identifying ability from the embedded SRAM. In addition to identification, we show that SRAM fingerprints capture noise, enabling true random number generation. We demonstrate that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.

Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers

https://engineering.purdue.edu/~ee650/downloads/NBTI-Ref1.pdf

A comprehensive model of PMOS NBTI degradation

Circuit failure prediction predicts the occurrence of a circuit failure before errors actually appear in system data and states. This is in contrast to classical error detection where a failure is detected after errors appear in system data and states. Circuit failure prediction is performed during system operation by analyzing the data collected by sensors inserted at various locations inside a chip. We demonstrate this concept of circuit failure prediction for a dominant PMOS aging mechanism induced by negative bias temperature instability (NBTI). NBTI-induced PMOS aging slows down PMOS transistors over time. As a result, the speed of a chip can significantly degrade over time and can result in delay faults. The traditional practice is to incorporate worst-case speed margins to prevent delay faults during system operation due to NBTI aging. A new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost. Simulation results using 90nm and 65nm technologies demonstrate that this technique can significantly improve system performance by enabling close to best-case design instead of traditional worst-case design.

Circuit Failure Prediction and Its Application to Transistor Aging

In this chapter, direct characterization techniques have been used to access the trap generation and trapping subcomponents of BTI degradation in HKMG MOSFETs having different gate stack processes. Generation of new traps is estimated using DCIV for NBTI stress and both DCIV and SILC for PBTI stress respectively in p- and n-channel MOSFETs. Flicker noise is used to estimate the density of process related pre-existing gate insulator traps responsible for hole and electron trapping respectively during NBTI and PBTI stress. The spatial and energetic locations of generated traps for NBTI and PBTI stress are identified. The time, bias, and temperature dependencies of trap generation obtained using the DCIV technique are compared between NBTI and PBTI stress, while these parameters obtained using DCIV and SILC techniques are compared for PBTI stress. The relative dominance of trap generation and trapping on NBTI and PBTI threshold voltage degradation is estimated for different gate insulator processes.

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

Scaling prospects of pre-cycled 2-bit channel engineered SONOS flash EEPROM cells are studied on cells co-doped with compensation and halo implant. The compensation implant is shown to work in long channel cells to optimize bit coupling, read disturb, and program speed. However, co-doping with compensation implant fails at short channel length to reduce read disturb thus bit coupling at safe read V D . The junction engineering scheme is shown as the possible alternative for successful scaling of cells to simultaneously reduce read disturb and bit coupling but at the expense of program speed, which seems detrimental for deep scaling of cells.

A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells

Negative and Positive Bias Temperature Instabilities (NBTI, PBTI) respectively in P and N channel High-K Metal Gate (HKMG) MOSFETs are modeled by trap generation (TG) and charge trapping (CT) and validated against measured data. The mechanism of TG (interface) is incorporated into TCAD and is separately validated using independent experiments. BTI kinetics is modeled at different stress bias (V G ) and temperature (T). Impacts of Nitrogen (N%) and Equivalent Oxide Thickness (EOT) scaling on the magnitude of BTI and its time, VG and T dependencies are modeled.

TCAD Incorporation of Physical Framework to Model N and P BTI in MOSFETs

We present a physical model of non-ohmic shunt current in a-Si:H p-i-n solar cells, and validate it with detailed measurements. This model is based on space-charge-limited (SCL) transport through localized p-i-p shunt paths, which can arise from contact metal incorporation in a-Si:H layer. This model explains both the electrical characteristics and the metastable switching behavior of the shunts within an integrated framework. We first verify the SCL model using simulations and statistically robust measurements, and then use this picture to analyze our systematic observations of non-volatile switching in these shunts. Our work not only resolves broad experimental observations on shunt behavior, but also suggests possible techniques for alleviating shunt induced performance and reliability issues.

A physical model for non-ohmic shunt conduction and metastability in amorphous silicon p-i-n solar cells

In this chapter, the BAT framework presented in Chap. 4 through Chap. 6 is used to analyze and model the impact of device dimension scaling on NBTI in Silicon and Silicon Germanium channel FinFETs and Silicon channel GAA-SNS FETs with RMG HKMG gate insulator stack. The modeling is done on ultra-fast measured NBTI time kinetics in devices having different fin or sheet dimensions (length and width). The scaling of device dimensions changes the mechanical stress-induced compressive strain in the channel, which is verified using TCAD simulations. This impacts the magnitude of NBTI and its voltage dependence. Different manifestations are observed for the (110) sidewall dominated FinFETs and (100) top surface dominated GAA-SNS FETs. The observed differences are explained using band structure calculations. The impact of dimension scaling on the extrapolated EOL degradation under use conditions is determined by the calibrated BAT framework.

Souvik Mahapatra

Papers

Physical Mechanism of BTI Degradation—Direct Estimation of Trap Generation and Trapping

A comprehensive analysis on scaling prospects of dual-bit channel engineered SONOS NOR-flash EEPROM cells

TCAD Incorporation of Physical Framework to Model N and P BTI in MOSFETs

A physical model for non-ohmic shunt conduction and metastability in amorphous silicon p-i-n solar cells

BAT Framework Modeling of Dimension Scaling in FinFETs and GAA-SNS FETs