Souvik Mahapatra

TL;DR: In this article, a novel simulation framework is developed to study NBTI variability in devices and SRAM circuits, where the stochastic reaction diffusion (RD) model for interface trap generation (ΔNIT) and the Stochastic 2 well model for charging of pre-existing bulk traps ( ΔNHT) are interfaced with TCAD for electrostatics and time-zero variability to determine variable NBTIs in device level.

TL;DR: In this article, different characterization methods are discussed to determine BTI degradation of MOSFET parameters and to directly estimate the pre-existing and generated gate insulator defects responsible for BTI.

TL;DR: In this article, the performance and reliability of charge trap flash with single and bi-layer Si-rich and N-rich nitride as the storage node is studied, and the effect of varying the SiON interfacial layer position on memory window and reliability is investigated.

TL;DR: In this paper, the degradation of planar high-k metal gate p-and n-channel MOSFETs under negative bias temperature instability (NBTI) and positive bias temperature stability (PBTI), respectively, was studied using different characterization methods.

TL;DR: In this article, a comprehensive review and reanalysis of experimental hot carrier degradation data in various MOSFET architectures is presented, where the universality of time kinetics and voltage acceleration of degradation, obtained using multiple measurement techniques, is analyzed for OFF-and different ON-state modes in long and short channel planar and drain extended MOS-FETs and FinFET.