Light-Emitting Diodes. (Monographs in Electrical and Electronic Engineering.) By A. A. Bergh and P. J. Dean. Pp. viii+591. (Clarendon: Oxford; Oxford University: London, 1976.) £22.

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Light-emitting diodes

Lasing is experimentally demonstrated in a direct bandgap GeSn alloy, grown directly onto Si(001). The authors observe a clear lasing threshold as well as linewidth narrowing at low temperatures.

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Lasing in direct-bandgap GeSn alloy grown on Si

Silicon photonics research can be dated back to the 1980s. However, the previous decade has witnessed an explosive growth in the field. Silicon photonics is a disruptive technology that is poised to revolutionize a number of application areas, for example, data centers, high-performance computing and sensing. The key driving force behind silicon photonics is the ability to use CMOS-like fabrication resulting in high-volume production at low cost. This is a key enabling factor for bringing photonics to a range of technology areas where the costs of implementation using traditional photonic elements such as those used for the telecommunications industry would be prohibitive. Silicon does however have a number of shortcomings as a photonic material. In its basic form it is not an ideal material in which to produce light sources, optical modulators or photodetectors for example. A wealth of research effort from both academia and industry in recent years has fueled the demonstration of multiple solutions to these and other problems, and as time progresses new approaches are increasingly being conceived. It is clear that silicon photonics has a bright future. However, with a growing number of approaches available, what will the silicon photonic integrated circuit of the future look like? This roadmap on silicon photonics delves into the different technology and application areas of the field giving an insight into the state-of-the-art as well as current and future challenges faced by researchers worldwide. Contributions authored by experts from both industry and academia provide an overview and outlook for the silicon waveguide platform, optical sources, optical modulators, photodetectors, integration approaches, packaging, applications of silicon photonics and approaches required to satisfy applications at mid-infrared wavelengths. Advances in science and technology required to meet challenges faced by the field in each of these areas are also addressed together with predictions of where the field is destined to reach.

https://iopscience.iop.org/article/10.1088/2040-8978/18/7/073003/pdf

Roadmap on silicon photonics

Hybrid silicon lasers based on bonded III–V layers on silicon are currently the best contenders for on-chip lasers for silicon photonics. On-chip silicon light sources are highly desired for use as electrical-to-optical converters in silicon-based photonics. Zhiping Zhou and Bing Yin of Peking University in China and Jurgen Michel of Massachusetts Institute of Technology assess the three main contenders for such light sources: erbium-based light sources, germanium-on-silicon lasers and III-V-based silicon lasers. They consider operating wavelength, pumping conditions, power consumption, thermal stability and fabrication process. The scientists regard the power efficiencies of electrically pumped erbium-based lasers as being too low and the threshold currents of germanium lasers as being too high. They conclude that III–V quantum dot lasers monolithically grown on silicon show the most promise for realizing on-chip lasers.

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On-chip light sources for silicon photonics

Abstract The emergence of silicon photonics over the past two decades has established silicon as a preferred substrate platform for photonic integration. While most silicon-based photonic components have so far been realized in the near-infrared (near-IR) telecommunication bands, the mid-infrared (mid-IR, 2–20-μm wavelength) band presents a significant growth opportunity for integrated photonics. In this review, we offer our perspective on the burgeoning field of mid-IR integrated photonics on silicon. A comprehensive survey on the state-of-the-art of key photonic devices such as waveguides, light sources, modulators, and detectors is presented. Furthermore, on-chip spectroscopic chemical sensing is quantitatively analyzed as an example of mid-IR photonic system integration based on these basic building blocks, and the constituent component choices are discussed and contrasted in the context of system performance and integration technologies.

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Mid-infrared integrated photonics on silicon: a perspective

In this paper, robustness and reliability differences related to the performance of the gate oxide of commercially-available 1200 V-rated planar and trench SiC MOSFETs have been investigated. Due to a thin gate oxide in SiC MOSFETs and to a naturally imperfect interface of the oxide layer (SiO2) with the SiC material, its quality and reliability become very important and could be a limiting factor of the SiC technology when compared to the Si one. A dedicated gate oxide step-by-step (VG SbS) tester has been prepared during which the gate voltage is varied with different profiles. Results of Fowler-Nordheim (FN), Time Dependent Dielectric Breakdown (TDDB) and three test runs of the VG SbS are presented in this paper. Both technologies show good reliability figures to allow the use in the application. Trench technology shows higher robustness limits whereas the extrapolated reliability at the rated gate voltage is superior for the planar one.

High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs

We demonstrate a very-low temperature cleaning technique based on atomic hydrogen irradiation for highly (1%) tensile strained Ge epilayers grown on metastable, partially strain relaxed GeSn buffer layers. Atomic hydrogen is obtained by catalytic cracking of hydrogen gas on a hot tungsten filament in an ultra-high vacuum chamber. X-ray photoemission spectroscopy, reflection high energy electron spectroscopy, atomic force microscopy, secondary ion mass spectroscopy, and micro-Raman showed that an O- and C-free Ge surface was achieved, while maintaining the same roughness and strain condition of the as-deposited sample and without any Sn segregation, at a process temperature in the 100–300 °C range.

/pdf/epi-cleaning-of-ge-gesn-heterostructures-4pdhz8wtg1.pdf

Epi-cleaning of Ge/GeSn heterostructures

We have recently developed a novel III-V integration scheme, where III-V material is grown
directly on top of Si within oxide nanotubes or microcavities which control the geometry of
nanostructures. This allows us to grow III-V material non-lattice matched on any crystalline
orientation of Si, to grow arbitrary shapes as well as abrupt heterojunctions, and to gain more
flexibility in tuning of composition. In this talk, applications for electronic devices such as
heterojunction tunnel FETs and microcavity III-V lasers monolithically integrated on Si will be
discussed along with an outlook for the future.

Monolithic integration of III-V nanostructures for electronic and photonic applications

The invention relates to a method for monolithic depositing a single-crystal, luminous in excitation, consisting of several elements of the IV main group IV-IV layer, in particular a GeSn or SiGeSn layer having a dislocation density less than 10 Providing a halide of a second IV element (B), for example, SnCl Heating the substrate are installed in crystalline order in the surface of a substrate temperature which is lower than the decomposition temperature of the pure hydride or a radical formed therefrom, and is sufficiently high that atoms of said first element (A) and the second element (B), wherein the substrate temperature is preferably in a range between 300 ° C and 475 ° C; Generating a carrier gas stream of an inert carrier gas, in particular N Transporting the hydride and the halide and any resulting degradation products to the surface at a total pressure of maximum 300 mbar; Depositing the IV-IV-layer or consisting of similar IV-IV layers layer sequence having a thickness of at least 200 nm, wherein the deposited layer has a Si

A method of depositing a crystal layer at low temperatures, in particular a photoluminescent IV-IV-IV-layer on a substrate, and a layer exhibiting such an optoelectronic component

The need to improve the electronic, thermo-electric or optic device performance as well as an all-Si based integration has significantly increased the requirements for Si/SiGe material. The introduction of strain in Si(Ge), which induces strong energy band modification and through this enhance carrier mobility and absorption/emission properties, has been the dominant technique to enhance the Si(Ge) device performance. However, the epitaxial growth of highly strained layers is very challenging, since growth at very low temperatures and with appropriate precursors is required. We will present epitaxial growth studies of pseudomorphic Si1-xGex and relaxed Ge layers on 200 mm Si(100) wafers using an AIXTRON Tricent® RPCVD tool. This is the first report of epitaxial Si(Ge) layer growth using an AIXTRON cold wall reactor with a showerhead technology. Compared to conventional CVD tools the consumption of precursors is strongly reduced. Using Si2H6 and Ge2H6 precursors with a flow of carrier gas (H2) of a maximum of 5 standard liters per minute epitaxial growth is obtained at temperatures as low as 425 °C at a constant growth pressure of 60 mbar. Prior to the epitaxial growth the wafers were cleaned using only O3/ vapor HF or O3/diluted HF/HCl which allows an in-situ pre-bake step at about 850°C (surface temperature). The layer thicknesses, composition and morphology were analyzed by RBS/C, XRD and TEM. Moreover Si/SiGe multi quantum well structures (MQW) with highly in-situ B-doped Si bottom and top layers (contacts) will be presented. B2H6 precursor was employed for in-situ doping. Photoluminescence (PL) and ToF-SIMS measurements were carried out to prove the high quality of the heterostructure. Fig. 1a shows the growth rate versus the Ge concentration up to 45at. % and the low channeling min. yield of the grown layers. The SiGe-layers were deposited at constant partial pressure of Si2H6 of 15 Pa at 600 °C. Up to 45at. % Ge the growth rate is linearly dependent on the Ge concentration and also the alloying increases linearly with the Ge2H6 partial pressure. RBS/Channeling measurements indicate single crystal quality with min. yield of 5% for strained Si1-xGex (0.15<x<0.4) with thicknesses up to 100 nm (Fig 1a). Hartmann et al. [1] showed that the critical thickness for plastic relaxation of SiGe can be increased compared to previous theories [2] by decreasing the deposition temperature. Their results can be seen in figure 1b. In our growth conditions we expect to further increase the critical thickness for plastic relaxation by using Si2H6 /Ge2H6 instead of SiH2Cl2 /GeH4 for deposition temperatures below 600 °C. The blue marked point in this plot represents a Si0.61Ge0.39 layer grown by our group at 600 °C. In Fig. 2a an XRD rocking curve of Si/SiGe MQW grown on SOI at 600 °C is shown. The MQW consists of a 4 times Si/Si0.67Ge0.33 (30 nm/10 nm) heterostructure. On top and below that heterostructure Si:B layers (100 nm) were deposited. The clear XRD peaks and the perfect matching with the simulated curve (red) indicate sharp interfaces. The inset of Fig. 2a showing the PL spectra at 5 K underline the high quality of the structure. B concentrations in the Si:B layers of about 1-5x1019cm-3 were extracted from sheet resistance measurements. In addition, ToF-SIMS analysis (Fig. 2b) indicate that the B concentration increases and decreases abruptly at the Si:B interfaces, respectively. The results for the low temperature Ge growth using Ge2H6 are shown in Fig. 3. Two different Ge2H6 flows are employed at temperatures between 375°C and 425°C. Growth rates up to 9 nm/min and root mean square (rms) values for the roughness of 1.5 nm are obtained for a growth temperature of 425°C.

Stephan Wirths

Papers

High Temperature Gate Voltage Step-by-Step Test to Assess Reliability Differences in 1200 V SiC MOSFETs

Epi-cleaning of Ge/GeSn heterostructures

Monolithic integration of III-V nanostructures for electronic and photonic applications

A method of depositing a crystal layer at low temperatures, in particular a photoluminescent IV-IV-IV-layer on a substrate, and a layer exhibiting such an optoelectronic component

Low Temperature RPCVD Epitaxial Growth of Si1-xGex and Ge Using Si2H6 and Ge2H6