Spintronic devices exploit the spin, as well as the charge, of electrons and could bring new capabilities to the microelectronics industry However, in order for spintronic devices to meet the ever-increasing demands of the industry, innovation in terms of materials, processes and circuits are required Here, we review recent developments in spintronics that could soon have an impact on the microelectronics and information technology industry We highlight and explore four key areas: magnetic memories, magnetic sensors, radio-frequency and microwave devices, and logic and non-Boolean devices We also discuss the challenges—at both the device and the system level—that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms This Review Article examines the potential of spintronics in four key areas of application —memories, sensors, microwave devices, and logic devices — and discusses the challenges that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms

Opportunities and challenges for spintronics in the microelectronics industry

Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT.

Magnetoresistive Random Access Memory: Present and Future

Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit torque (SOT), and electric field (E-field) effect on magnetic anisotropy. The NV memories using STT have been studied and developed most actively and are about to enter into the market by major semiconductor foundry companies. On the other hand, a development of the NV memories using other writing schemes are now underway. In this review article, first, the recent advancement of the spintronics device using STT and the NV memories using them are reviewed. Next, spintronics devices using the other two writing schemes (SOT and E-field) are briefly reviewed, including issues to be addressed for the NV memories application.

https://www.mdpi.com/2079-9268/8/4/44/pdf

A recent progress of spintronics devices for integrated circuit applications

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This article presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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Defect and Fault Modeling Framework for STT-MRAM Testing

Spin-orbit torque (SOT) magnetic random access memory (MRAM) is an emerging non-volatile memory that offers efficient and reliable sub-ns switching. It is considered as a promising candidate to tackle the replacement of SRAM memories in low level caches (L1-3). In this paper, we review the fundamentals of spin-orbit torque and we describe full-scale integration of perpendicular magnetized SOT-MRAM devices on 300mm wafers, using manufacturable methods and CMOS compatible processes. We demonstrate state-of-the-art properties of W-based top-pinned magnetic tunnel junction (MTJ) with perpendicularly magnetic anisotropy (PMA) that possess large endurance (>1011), and that can be switched at subnanosecond regimes (210ps) with power as low as 130pJ on 60nm devices. We conclude by opening current research focus and recent progress made by our team.

Spin-Orbit Torque MRAM for ultrafast embedded memories: from fundamentals to large scale technology integration

We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.

T. Kitamura

Papers

22-nm FD-SOI Embedded MRAM with Full Solder Reflow Compatibility and Enhanced Magnetic Immunity