Rishikesh Krishnan

TL;DR: A fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization, designed to enable both High Performance Compute (HPC) and mobile applications.

TL;DR: 22-nm FD-SOI 40Mb embedded MRAM (eMRAM) macros for automotive-grade-l (Auto-G1) MCU applications are demonstrated and the effects of magnetic tunnel junction (MTJ) size on reliability and scalability of eMRAM technology beyond 22 nm are examined.

TL;DR: A fully functional embedded MRAM macro integrated into a 22-nm FD-SOI CMOS platform and showing intrinsic stand-by magnetic immunity of 1.4 kOe reveals that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.

TL;DR: In this paper, a semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspension channel structure, is presented, where the source and drain structures are in contact with the region ends of the suspended channel through a silicon cladding layer.

TL;DR: In this paper, a method for producing a semiconductor structure, as well as a semiconducting structure, that uses a partial removal of an insulating layer around the semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layers.