Showing papers by "Tanay Karnik published in 2005"
TL;DR: In this article, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mV/sub P-P/output droop with only a small on-chip decoupling capacitor of 0.6 nF.
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.
509 citations
TL;DR: An integrated buck dc-dc converter for multi-V/sub CC/ microprocessors with four-phase topology and fast hysteretic control is demonstrated, which eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip.
Abstract: We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.
299 citations
13 Jun 2005
TL;DR: Effective logic soft error protection requires solutions to the following three problems: accurate soft error rate estimation for combinational logic networks; automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected.
Abstract: Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) accurate soft error rate estimation for combinational logic networks; (2) automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) new cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.
99 citations
Patent•
21 Jun 2005TL;DR: In this paper, a method of programming a memory array, including accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, is presented, each device being programmed by breaking a dielectric layer of the device.
Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.
39 citations
Patent•
01 Sep 2005TL;DR: In this article, a coupled inductor topology for the multi-phase transformers comprising N primary inductors (210-240) is described, where each primary inductor is coupled to one of N input nodes and a common output node (205).
Abstract: A method and apparatus for multi-phase transformers (200) are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors (210-240). In one embodiment, each primary inductor is coupled to one of N input nodes (201-1, 201-2, 201-3, 201-4) and a common output node (205). The transformer further includes N-1 secondary inductors (222-242) coupled in series between one input node (201-1) and the common output node (250). In one embodiment, the N-1 secondary inductors (222-242) are arranged to couple energy from N-1 of the primary inductors (220-240) to provide a common node voltage (250) as an average of N input node voltages (201-1, 201-2, 201-3, 201-4), wherein N is an integer greater than two. Other embodiments are described and claimed.
32 citations
Proceedings Article•
01 Jan 2005
TL;DR: In this paper, the authors demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology, which enables a 90 mVp-p output droop for a 100mA load step with only a small on-chip decoupling capacitor of 0.6 nF.
Abstract: We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mVp-p output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm 2 and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm 2 .
24 citations
Patent•
28 Jun 2005TL;DR: In this article, a temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
Abstract: A temperature-independent voltage reference containing two independent bias circuits powered by the reference voltage, each bias circuit containing components with an exponential dependence of current on voltage and one containing a resistive impedance, and further including voltage dividers and an active component.
22 citations
Patent•
27 Jun 2005Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
14 citations
Patent•
30 Jun 2005TL;DR: In this article, a voltage droop detector is proposed to capture the very highfrequency noise on the power grid of a load, such as a microprocessor, by sampling the voltages frequently enough to ensure that all droop events are captured.
Abstract: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0 th droop, as well as 1 st droops, 2 nd droops, and so on, are captured and stored for subsequent analysis. The circuits sample the voltages frequently enough to ensure that all droop events are captured. Other embodiments are described and claimed.
13 citations
Patent•
27 Jun 2005TL;DR: In this paper, error is sensed in a voltage at an output node and one or more analog signals are generated based on the sensed error, which are then converted into digital signals.
Abstract: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.
12 citations
Patent•
31 Mar 2005TL;DR: In this paper, a plurality of current sink elements coupled between a power supply and a reference potential are configured to enable the current sink devices to sink current, and selection inputs are configurable to control the state of the multiplexers.
Abstract: One disclosed system includes a plurality of current sink elements coupled between a power supply and a reference potential. A plurality of multiplexers are configured to enable the current sink elements to sink current, and a plurality of selection inputs are configured to control the state of the multiplexers.
Patent•
31 Mar 2005TL;DR: In this article, a reference signal is distributed to die locations proximal to the signals to be measured, and the relative delay between the signals can be calculated using the reference signal measurements.
Abstract: Systems and methods are disclosed for measuring signals on an integrated circuit die. In one embodiment, a reference signal is distributed to die locations proximal to the signals to be measured. The reference signal is transmitted over transport paths coupling each of the signals to be measured to the die output. The signals to be measured are transmitted over their respective transport paths and measured at the die output. The relative delay between the signals can be calculated using the reference signal measurements.
Patent•
31 Jan 2005TL;DR: In this article, the authors describe an apparatus for shifting a low swing signal, which includes a first pair of transistors to receive a first input signal and a second input signal, and to generate a first output signal that is a shifted version of the first input signals.
Abstract: In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first input signal. The apparatus further includes a second pair of transistors to receive the first input signal and the second input signal and to generate a second output signal that is a shifted version of the second input signal.
Patent•
01 Sep 2005TL;DR: In this paper, a serienparallel gekoppelte Spulentopologie aus Primarspulen (210, 220, 230, 240) and Sekundarspules (222, 232, 242, 242) was umfasst.
Abstract: Transformator, der umfasst: eine serienparallel gekoppelte Spulentopologie aus Primarspulen (210, 220, 230, 240) und Sekundarspulen (222, 232, 242), die so angeordnet sind, dass sie eine gemeinsame Knotenspannung als einen Mittelwert von N Eingangsknotenspannungen bereitstellen, wobei N eine ganze Zahl groser als zwei ist, und mindestens zwei Sekundarspulen in Serie gekoppelt sind, wobei die serienparallel gekoppelte Spulentopologie umfasst: N Primarspulen (210, 220, 230, 240), wobei jede der Primarspulen elektrisch an jeweils einen von N Eingangsknoten (201-1–201-4) und einen gemeinsamen Ausgangsknoten (250) gekoppelt ist; und N – 1 Sekundarspulen (222, 232, 242), die elektrisch in Serie zwischen einen Eingangsknoten und den gemeinsamen Ausgangsknoten (250) gekoppelt sind, wobei die N – 1 Sekundarspulen (222, 232, 242) so angeordnet sind, dass sie induktiv Energie von N – 1 der Primarspulen (220, 230, 240) koppeln.