Showing papers by "Teresa Riesgo published in 2016"

Towards reliable optical label-free point-of-care (PoC) biosensing devices

Abstract: In this work, we report a method to read-out optical biosensors that significantly enhance the Limit of Detection (LoD). In a previous work we introduced the concept of “Increased Relative Optical Power” (IROP), related to the interferometric optical signals of two interferometers as a biosensing method to measure biological species [1] (Holgado et al., 2014). We predicted that this theory might have important implications for developing compact Point of Care (PoC) devices with a significant improvement in the LoD. Moreover, this method can be used for reading-out most of the optical transducers reported in the literature. While in that first study we demonstrated theoretically and experimentally this novel concept by using a conventional high-resolution spectrometer, in this article we report the performance of a novel compact PoC device specifically developed on IROP principle to demonstrate these expected predictions. This improvement in the performance is shown: Firstly by measuring a set of chips simulating thin biofilm thicknesses and fabricated by atomic layer deposition (ALD), and secondly by carrying out a direct immunoassay based on the complex anti-IgG/IgG. Finally, both results are compared with standard high-resolution spectrometry. The main conclusion is that this novel compact PoC based on IROP concept considerably enhance the LoD and performance in a cost-effective manner.

Power analysis approach and its application to IP-based SoC design

Abstract: Purpose – Low-power consumption has become an important issue that cannot be ignored in system-on-chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. The purpose of this paper is to demonstrate an accurate and fast power estimation technique. Design/methodology/approach – The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings – The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of...

Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project

Abstract: In this article we present the main results obtained in the ARTEMIS-JU WSN-DPCM project between October 2011 and September 2015. The first objective of the project was the development of an integrated toolset for Wireless sensor networks (WSN) application planning, development, commissioning and maintenance, which aims to support application domain experts, with limited WSN expertise, to efficiently develop WSN applications from planning to lifetime maintenance. The toolset is made of three main tools: one for planning, one for application development and simulation (which can include hardware nodes), and one for network commissioning and lifetime maintenance. The tools are integrated in a single platform which promotes software reuse by automatically selecting suitable library components for application synthesis and the abstraction of the underlying architecture through the use of a middleware layer. The second objective of the project was to test the effectiveness of the toolset for the development of two case studies in different domains, one for detecting the occupancy state of parking lots and one for monitoring air concentration of harmful gasses near an industrial site.

A scalable H.264/AVC deblocking filter architecture

Abstract: The deblocking filter (DF) is one of the most complex functional cores of the H.264/AVC and SVC codecs. Its computational cost is heavily dependent on the video profile and the selected scalability level. With the goal of providing faster and better solutions, developers are focused on designing hardware architectures. Thus, it is possible taking advantage of multitasking, reusability and parallelization techniques. In this context, this work proposes a scalable DF architecture that is able to adapt its structure and performance to different video configurations, due to its modular and regular structure. The scalability feature avoids redesigning the whole architecture in case of the environmental demands or the configuration settings change. These facts mean savings in terms of design productivity and silicon area by adapting the necessary logical resources to each condition. Furthermore, regarding the data dependences involved in the H.264/AVC DF algorithm, the proposed architecture relies on an improved version of a traditional wavefront parallelization strategy, also proposed by the authors. This solution reduces the amount of clock cycles needed to filter a video frame as compared to traditional strategies. Implementation results, in an FPGA Virtex-5, demonstrate the performance benefits of this flexible solution as compared to some rigid state-of-the-art deblocking filter approaches.

Teaching hybrid HW/SW embedded system design using FPGA-based devices

Abstract: Complex computing platforms involving pipelined processors, memory hierarchies, multi-core and many-core architectures are very common nowadays. These approaches require a deep understanding of the underlying hardware and the corresponding programing model to be able to decide which alternative is more suitable, i.e. obtain the best performance at the minimum cost, for a given application. Hence, it is important to cover all these aspects in academic curricula in order to provide engineers with competitive advantages and increase industrial productivity. In this paper, the methodology followed in a subject on Advanced Processing Architectures from a MSc program is presented. The theoretical content is complemented using hands-on exercises to further analyze the concepts discussed in class. As an example, the practical lessons on single-core Systems on Programmable Chip are reviewed in detail, showing the key ideas that are to be acquired by the students enrolled in the subject. Moreover, the proposed strategy has been evaluated using a voluntary and anonymous questionnaire to detect the strong and weak points of the proposed approach. This feedback is essential to provide students with valuable knowledge and meet quality criteria in academic education.

Teaching wireless sensor networks to master and PhD students based on the cookie node

Abstract: Wireless Sensor Networks (WSNs) have evolved during the last decade, becoming an accessible technology in the market nowadays. Even cutting edge state of the art works are still being carried out in universities and research centers and departments, the curriculum of communication, computer science and electronic engineers lacks of contents related to specific disciplines inherent to WSNs field. The skills needed to face de development of applications based on WSNs are varied, and traditional engineering courses do not cover the required contents. In this paper, a new approach for teaching Wireless Sensor Networks for students within the Research Master on Industrial Electronics at Universidad Politecnica de Madrid (UPM), Spain, is presented, considering the challenges imposed by the European Higher Education Area. The course is both theoretical and practical, focusing on the real problems of deploying WSNs in real applications, covering aspects related to software development, hardware platforms and communication protocols.